* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
- * License along with this library; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA 02110-1301 USA
+ * License along with this library; if not, see <http://www.gnu.org/licenses/>
*/
#include "hw.h"
#include "pc.h"
+#include "pci.h"
+#include "msix.h"
#include "qemu-timer.h"
#include "host-utils.h"
+#include "kvm.h"
//#define DEBUG_APIC
#define MAX_APICS 255
#define MAX_APIC_WORDS 8
+/* Intel APIC constants: from include/asm/msidef.h */
+#define MSI_DATA_VECTOR_SHIFT 0
+#define MSI_DATA_VECTOR_MASK 0x000000ff
+#define MSI_DATA_DELIVERY_MODE_SHIFT 8
+#define MSI_DATA_TRIGGER_SHIFT 15
+#define MSI_DATA_LEVEL_SHIFT 14
+#define MSI_ADDR_DEST_MODE_SHIFT 2
+#define MSI_ADDR_DEST_ID_SHIFT 12
+#define MSI_ADDR_DEST_ID_MASK 0x00ffff0
+
+#define MSI_ADDR_BASE 0xfee00000
+#define MSI_ADDR_SIZE 0x100000
+
typedef struct APICState {
CPUState *cpu_env;
uint32_t apicbase;
int64_t initial_count_load_time, next_time;
uint32_t idx;
QEMUTimer *timer;
+ int sipi_vector;
+ int wait_for_sipi;
} APICState;
static int apic_io_memory;
static int apic_irq_delivered;
-static void apic_init_ipi(APICState *s);
static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
static void apic_update_irq(APICState *s);
static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
case APIC_DM_INIT:
/* normal INIT IPI sent to processors */
foreach_apic(apic_iter, deliver_bitmask,
- apic_init_ipi(apic_iter) );
+ cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
return;
case APIC_DM_EXTINT:
}
-static void apic_init_ipi(APICState *s)
+void apic_init_reset(CPUState *env)
{
+ APICState *s = env->apic_state;
int i;
+ if (!s)
+ return;
+
s->tpr = 0;
s->spurious_vec = 0xff;
s->log_dest = 0;
s->initial_count = 0;
s->initial_count_load_time = 0;
s->next_time = 0;
+ s->wait_for_sipi = 1;
- cpu_reset(s->cpu_env);
-
- s->cpu_env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
+ env->halted = !(s->apicbase & MSR_IA32_APICBASE_BSP);
}
-/* send a SIPI message to the CPU to start it */
static void apic_startup(APICState *s, int vector_num)
{
- CPUState *env = s->cpu_env;
- if (!env->halted)
+ s->sipi_vector = vector_num;
+ cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
+}
+
+void apic_sipi(CPUState *env)
+{
+ APICState *s = env->apic_state;
+
+ cpu_reset_interrupt(env, CPU_INTERRUPT_SIPI);
+
+ if (!s->wait_for_sipi)
return;
+
env->eip = 0;
- cpu_x86_load_seg_cache(env, R_CS, vector_num << 8, vector_num << 12,
+ cpu_x86_load_seg_cache(env, R_CS, s->sipi_vector << 8, s->sipi_vector << 12,
0xffff, 0);
env->halted = 0;
+ s->wait_for_sipi = 0;
}
static void apic_deliver(APICState *s, uint8_t dest, uint8_t dest_mode,
return val;
}
+static void apic_send_msi(target_phys_addr_t addr, uint32 data)
+{
+ uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
+ uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
+ uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
+ uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
+ uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
+ /* XXX: Ignore redirection hint. */
+ apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
+}
+
static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
{
CPUState *env;
APICState *s;
- int index;
+ int index = (addr >> 4) & 0xff;
+ if (addr > 0xfff || !index) {
+ /* MSI and MMIO APIC are at the same memory location,
+ * but actually not on the global bus: MSI is on PCI bus
+ * APIC is connected directly to the CPU.
+ * Mapping them on the global bus happens to work because
+ * MSI registers are reserved in APIC MMIO and vice versa. */
+ apic_send_msi(addr, val);
+ return;
+ }
env = cpu_single_env;
if (!env)
printf("APIC write: %08x = %08x\n", (uint32_t)addr, val);
#endif
- index = (addr >> 4) & 0xff;
switch(index) {
case 0x02:
s->id = (val >> 24);
s->apicbase = 0xfee00000 |
(bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
- apic_init_ipi(s);
+ cpu_reset(s->cpu_env);
+ apic_init_reset(s->cpu_env);
if (bsp) {
/*
*/
s->lvt[APIC_LVT_LINT0] = 0x700;
}
+
+ cpu_synchronize_state(s->cpu_env, 1);
}
static CPUReadMemoryFunc *apic_mem_read[3] = {
s->cpu_env = env;
apic_reset(s);
+ msix_supported = 1;
/* XXX: mapping more APICs at the same memory location */
if (apic_io_memory == 0) {
on the global memory bus. */
apic_io_memory = cpu_register_io_memory(apic_mem_read,
apic_mem_write, NULL);
- cpu_register_physical_memory(s->apicbase & ~0xfff, 0x1000,
+ /* XXX: what if the base changes? */
+ cpu_register_physical_memory(MSI_ADDR_BASE, MSI_ADDR_SIZE,
apic_io_memory);
}
s->timer = qemu_new_timer(vm_clock, apic_timer, s);
register_savevm("apic", s->idx, 2, apic_save, apic_load, s);
- qemu_register_reset(apic_reset, 0, s);
+ qemu_register_reset(apic_reset, s);
local_apics[s->idx] = s;
return 0;
}
-
projects / qemu.git / blobdiff