#include "hw/firmware/smbios.h"
#include "qapi/visitor.h"
#include "qapi/qapi-visit-common.h"
+#include "qapi/qmp/qlist.h"
#include "standard-headers/linux/input.h"
#include "hw/arm/smmuv3.h"
#include "hw/acpi/acpi.h"
+#include "target/arm/cpu-qom.h"
#include "target/arm/internals.h"
+#include "target/arm/multiprocessing.h"
+#include "target/arm/gtimer.h"
#include "hw/mem/pc-dimm.h"
#include "hw/mem/nvdimm.h"
#include "hw/acpi/generic_event_device.h"
[VIRT_PLATFORM_BUS] = 112, /* ...to 112 + PLATFORM_BUS_NUM_IRQS -1 */
};
-static const char *valid_cpus[] = {
-#ifdef CONFIG_TCG
- ARM_CPU_TYPE_NAME("cortex-a7"),
- ARM_CPU_TYPE_NAME("cortex-a15"),
- ARM_CPU_TYPE_NAME("cortex-a35"),
- ARM_CPU_TYPE_NAME("cortex-a55"),
- ARM_CPU_TYPE_NAME("cortex-a72"),
- ARM_CPU_TYPE_NAME("cortex-a76"),
- ARM_CPU_TYPE_NAME("cortex-a710"),
- ARM_CPU_TYPE_NAME("a64fx"),
- ARM_CPU_TYPE_NAME("neoverse-n1"),
- ARM_CPU_TYPE_NAME("neoverse-v1"),
- ARM_CPU_TYPE_NAME("neoverse-n2"),
-#endif
- ARM_CPU_TYPE_NAME("cortex-a53"),
- ARM_CPU_TYPE_NAME("cortex-a57"),
- ARM_CPU_TYPE_NAME("host"),
- ARM_CPU_TYPE_NAME("max"),
-};
-
-static bool cpu_type_valid(const char *cpu)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(valid_cpus); i++) {
- if (strcmp(cpu, valid_cpus[i]) == 0) {
- return true;
- }
- }
- return false;
-}
-
static void create_randomness(MachineState *ms, const char *node)
{
struct {
for (cpu = 0; cpu < smp_cpus; cpu++) {
ARMCPU *armcpu = ARM_CPU(qemu_get_cpu(cpu));
- if (armcpu->mp_affinity & ARM_AFF3_MASK) {
+ if (arm_cpu_mp_affinity(armcpu) & ARM_AFF3_MASK) {
addr_cells = 2;
break;
}
if (addr_cells == 2) {
qemu_fdt_setprop_u64(ms->fdt, nodename, "reg",
- armcpu->mp_affinity);
+ arm_cpu_mp_affinity(armcpu));
} else {
qemu_fdt_setprop_cell(ms->fdt, nodename, "reg",
- armcpu->mp_affinity);
+ arm_cpu_mp_affinity(armcpu));
}
if (ms->possible_cpus->cpus[cs->cpu_index].props.has_node_id) {
if (vms->virt) {
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
+ GIC_FDT_IRQ_TYPE_PPI,
+ INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
} else {
2, vms->memmap[VIRT_GIC_VCPU].base,
2, vms->memmap[VIRT_GIC_VCPU].size);
qemu_fdt_setprop_cells(ms->fdt, nodename, "interrupts",
- GIC_FDT_IRQ_TYPE_PPI, ARCH_GIC_MAINT_IRQ,
+ GIC_FDT_IRQ_TYPE_PPI,
+ INTID_TO_PPI(ARCH_GIC_MAINT_IRQ),
GIC_FDT_IRQ_FLAGS_LEVEL_HI);
}
}
}
if (vms->gic_version != VIRT_GIC_VERSION_2) {
+ QList *redist_region_count;
uint32_t redist0_capacity = virt_redist_capacity(vms, VIRT_GIC_REDIST);
uint32_t redist0_count = MIN(smp_cpus, redist0_capacity);
nb_redist_regions = virt_gicv3_redist_region_count(vms);
- qdev_prop_set_uint32(vms->gic, "len-redist-region-count",
- nb_redist_regions);
- qdev_prop_set_uint32(vms->gic, "redist-region-count[0]", redist0_count);
+ redist_region_count = qlist_new();
+ qlist_append_int(redist_region_count, redist0_count);
+ if (nb_redist_regions == 2) {
+ uint32_t redist1_capacity =
+ virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
+
+ qlist_append_int(redist_region_count,
+ MIN(smp_cpus - redist0_count, redist1_capacity));
+ }
+ qdev_prop_set_array(vms->gic, "redist-region-count",
+ redist_region_count);
if (!kvm_irqchip_in_kernel()) {
if (vms->tcg_its) {
qdev_prop_set_bit(vms->gic, "has-lpi", true);
}
}
-
- if (nb_redist_regions == 2) {
- uint32_t redist1_capacity =
- virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2);
-
- qdev_prop_set_uint32(vms->gic, "redist-region-count[1]",
- MIN(smp_cpus - redist0_count, redist1_capacity));
- }
} else {
if (!kvm_irqchip_in_kernel()) {
qdev_prop_set_bit(vms->gic, "has-virtualization-extensions",
clustersz = GICV3_TARGETLIST_BITS;
}
}
- return arm_cpu_mp_affinity(idx, clustersz);
+ return arm_build_mp_affinity(idx, clustersz);
}
static inline bool *virt_get_high_memmap_enabled(VirtMachineState *vms,
/* Base address of the high IO region */
memtop = base = device_memory_base + ROUND_UP(device_memory_size, GiB);
if (memtop > BIT_ULL(pa_bits)) {
- error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes\n",
- pa_bits, memtop - BIT_ULL(pa_bits));
+ error_report("Addressing limited to %d bits, but memory exceeds it by %llu bytes",
+ pa_bits, memtop - BIT_ULL(pa_bits));
exit(EXIT_FAILURE);
}
if (base < device_memory_base) {
if (pmu) {
assert(arm_feature(&ARM_CPU(cpu)->env, ARM_FEATURE_PMU));
if (kvm_irqchip_in_kernel()) {
- kvm_arm_pmu_set_irq(cpu, VIRTUAL_PMU_IRQ);
+ kvm_arm_pmu_set_irq(ARM_CPU(cpu), VIRTUAL_PMU_IRQ);
}
- kvm_arm_pmu_init(cpu);
+ kvm_arm_pmu_init(ARM_CPU(cpu));
}
if (steal_time) {
- kvm_arm_pvtime_init(cpu, pvtime_reg_base +
- cpu->cpu_index * PVTIME_SIZE_PER_CPU);
+ kvm_arm_pvtime_init(ARM_CPU(cpu), pvtime_reg_base
+ + cpu->cpu_index
+ * PVTIME_SIZE_PER_CPU);
}
}
} else {
unsigned int smp_cpus = machine->smp.cpus;
unsigned int max_cpus = machine->smp.max_cpus;
- if (!cpu_type_valid(machine->cpu_type)) {
- error_report("mach-virt: CPU type %s not supported", machine->cpu_type);
- exit(1);
- }
-
possible_cpus = mc->possible_cpu_arch_ids(machine);
/*
virtio_md_pci_pre_plug(VIRTIO_MD_PCI(dev), MACHINE(hotplug_dev), errp);
} else if (object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI)) {
hwaddr db_start = 0, db_end = 0;
+ QList *reserved_regions;
char *resv_prop_str;
if (vms->iommu != VIRT_IOMMU_NONE) {
db_start, db_end,
VIRTIO_IOMMU_RESV_MEM_T_MSI);
- object_property_set_uint(OBJECT(dev), "len-reserved-regions", 1, errp);
- object_property_set_str(OBJECT(dev), "reserved-regions[0]",
- resv_prop_str, errp);
+ reserved_regions = qlist_new();
+ qlist_append_str(reserved_regions, resv_prop_str);
+ qdev_prop_set_array(dev, "reserved-regions", reserved_regions);
g_free(resv_prop_str);
}
}
{
MachineClass *mc = MACHINE_CLASS(oc);
HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(oc);
+ static const char * const valid_cpu_types[] = {
+#ifdef CONFIG_TCG
+ ARM_CPU_TYPE_NAME("cortex-a7"),
+ ARM_CPU_TYPE_NAME("cortex-a15"),
+#ifdef TARGET_AARCH64
+ ARM_CPU_TYPE_NAME("cortex-a35"),
+ ARM_CPU_TYPE_NAME("cortex-a55"),
+ ARM_CPU_TYPE_NAME("cortex-a72"),
+ ARM_CPU_TYPE_NAME("cortex-a76"),
+ ARM_CPU_TYPE_NAME("cortex-a710"),
+ ARM_CPU_TYPE_NAME("a64fx"),
+ ARM_CPU_TYPE_NAME("neoverse-n1"),
+ ARM_CPU_TYPE_NAME("neoverse-v1"),
+ ARM_CPU_TYPE_NAME("neoverse-n2"),
+#endif /* TARGET_AARCH64 */
+#endif /* CONFIG_TCG */
+#ifdef TARGET_AARCH64
+ ARM_CPU_TYPE_NAME("cortex-a53"),
+ ARM_CPU_TYPE_NAME("cortex-a57"),
+#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
+ ARM_CPU_TYPE_NAME("host"),
+#endif /* CONFIG_KVM || CONFIG_HVF */
+#endif /* TARGET_AARCH64 */
+ ARM_CPU_TYPE_NAME("max"),
+ NULL
+ };
mc->init = machvirt_init;
/* Start with max_cpus set to 512, which is the maximum supported by KVM.
#else
mc->default_cpu_type = ARM_CPU_TYPE_NAME("max");
#endif
+ mc->valid_cpu_types = valid_cpu_types;
mc->get_default_cpu_node_id = virt_get_default_cpu_node_id;
mc->kvm_type = virt_kvm_type;
assert(!mc->get_hotplug_handler);
}
type_init(machvirt_machine_init);
+static void virt_machine_9_0_options(MachineClass *mc)
+{
+}
+DEFINE_VIRT_MACHINE_AS_LATEST(9, 0)
+
static void virt_machine_8_2_options(MachineClass *mc)
{
+ virt_machine_9_0_options(mc);
+ compat_props_add(mc->compat_props, hw_compat_8_2, hw_compat_8_2_len);
}
-DEFINE_VIRT_MACHINE_AS_LATEST(8, 2)
+DEFINE_VIRT_MACHINE(8, 2)
static void virt_machine_8_1_options(MachineClass *mc)
{
projects / mirror_qemu.git / blobdiff