}
}
-static int gem_can_receive(VLANClientState *nc)
+static int gem_can_receive(NetClientState *nc)
{
GemState *s;
* gem_receive:
* Fit a packet handed to us by QEMU into the receive descriptor ring.
*/
-static ssize_t gem_receive(VLANClientState *nc, const uint8_t *buf, size_t size)
+static ssize_t gem_receive(NetClientState *nc, const uint8_t *buf, size_t size)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr, last_desc_addr;
+ hwaddr packet_desc_addr, last_desc_addr;
GemState *s;
unsigned rxbufsize, bytes_to_copy;
unsigned rxbuf_offset;
static void gem_transmit(GemState *s)
{
unsigned desc[2];
- target_phys_addr_t packet_desc_addr;
+ hwaddr packet_desc_addr;
uint8_t tx_packet[2048];
uint8_t *p;
unsigned total_bytes;
* gem_read32:
* Read a GEM register.
*/
-static uint64_t gem_read(void *opaque, target_phys_addr_t offset, unsigned size)
+static uint64_t gem_read(void *opaque, hwaddr offset, unsigned size)
{
GemState *s;
uint32_t retval;
* gem_write32:
* Write a GEM register.
*/
-static void gem_write(void *opaque, target_phys_addr_t offset, uint64_t val,
+static void gem_write(void *opaque, hwaddr offset, uint64_t val,
unsigned size)
{
GemState *s = (GemState *)opaque;
.endianness = DEVICE_LITTLE_ENDIAN,
};
-static void gem_cleanup(VLANClientState *nc)
+static void gem_cleanup(NetClientState *nc)
{
GemState *s = DO_UPCAST(NICState, nc, nc)->opaque;
s->nic = NULL;
}
-static void gem_set_link(VLANClientState *nc)
+static void gem_set_link(NetClientState *nc)
{
DB_PRINT("\n");
phy_update_link(DO_UPCAST(NICState, nc, nc)->opaque);