*/
#include "qemu/osdep.h"
-#include "hw/hw.h"
+#include "qemu/units.h"
+#include "hw/irq.h"
#include "hw/mips/mips.h"
#include "hw/sysbus.h"
+#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/log.h"
+#include "qemu/module.h"
#include "exec/address-spaces.h"
#include "trace.h"
+#include "qom/object.h"
/********************************************************/
/* rc4030 emulation */
#define DMA_FLAG_ADDR_INTR 0x0400
#define TYPE_RC4030 "rc4030"
-#define RC4030(obj) \
- OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
+OBJECT_DECLARE_SIMPLE_TYPE(rc4030State, RC4030)
+
+#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
+
+struct rc4030State {
-typedef struct rc4030State
-{
SysBusDevice parent;
uint32_t config; /* 0x0000: RC4030 config register */
qemu_irq jazz_bus_irq;
/* whole DMA memory region, root of DMA address space */
- MemoryRegion dma_mr;
+ IOMMUMemoryRegion dma_mr;
AddressSpace dma_as;
MemoryRegion iomem_chipset;
MemoryRegion iomem_jazzio;
-} rc4030State;
+};
static void set_next_tick(rc4030State *s)
{
- qemu_irq_lower(s->timer_irq);
uint32_t tm_hz;
+ qemu_irq_lower(s->timer_irq);
tm_hz = 1000 / (s->itr + 1);
case 0x0058:
val = s->cache_bmask;
/* HACK */
- if (s->cache_bmask == (uint32_t)-1)
+ if (s->cache_bmask == (uint32_t)-1) {
s->cache_bmask = 0;
+ }
break;
/* Remote Speed Registers */
case 0x0070:
pending = s->isr_jazz & s->imr_jazz;
- if (pending != 0)
+ if (pending != 0) {
qemu_irq_raise(s->jazz_bus_irq);
- else
+ } else {
qemu_irq_lower(s->jazz_bus_irq);
+ }
}
static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static IOMMUTLBEntry rc4030_dma_translate(MemoryRegion *iommu, hwaddr addr,
- bool is_write)
+static IOMMUTLBEntry rc4030_dma_translate(IOMMUMemoryRegion *iommu, hwaddr addr,
+ IOMMUAccessFlags flag, int iommu_idx)
{
rc4030State *s = container_of(iommu, rc4030State, dma_mr);
IOMMUTLBEntry ret = {
if (i < s->dma_tl_limit / sizeof(entry)) {
entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
if (address_space_read(ret.target_as, entry_address,
- MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry,
- sizeof(entry)) == MEMTX_OK) {
+ MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
+ == MEMTX_OK) {
ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
ret.perm = IOMMU_RW;
}
return ret;
}
-static const MemoryRegionIOMMUOps rc4030_dma_ops = {
- .translate = rc4030_dma_translate,
-};
-
static void rc4030_reset(DeviceState *dev)
{
rc4030State *s = RC4030(dev);
s->memory_refresh_rate = 0x18186;
s->nvram_protect = 7;
- for (i = 0; i < 15; i++)
+ for (i = 0; i < 15; i++) {
s->rem_speed[i] = 7;
+ }
s->imr_jazz = 0x10; /* XXX: required by firmware, but why? */
s->isr_jazz = 0;
static int rc4030_post_load(void *opaque, int version_id)
{
- rc4030State* s = opaque;
+ rc4030State *s = opaque;
set_next_tick(s);
update_jazz_irq(s);
}
};
-static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
+static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
+ int len, bool is_write)
{
rc4030State *s = opaque;
hwaddr dma_addr;
int dev_to_mem;
- s->dma_regs[n][DMA_REG_ENABLE] &= ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
+ s->dma_regs[n][DMA_REG_ENABLE] &=
+ ~(DMA_FLAG_TC_INTR | DMA_FLAG_MEM_INTR | DMA_FLAG_ADDR_INTR);
/* Check DMA channel consistency */
dev_to_mem = (s->dma_regs[n][DMA_REG_ENABLE] & DMA_FLAG_MEM_TO_DEV) ? 0 : 1;
}
/* Get start address and len */
- if (len > s->dma_regs[n][DMA_REG_COUNT])
+ if (len > s->dma_regs[n][DMA_REG_COUNT]) {
len = s->dma_regs[n][DMA_REG_COUNT];
+ }
dma_addr = s->dma_regs[n][DMA_REG_ADDRESS];
/* Read/write data at right place */
void rc4030_dma_read(void *dma, uint8_t *buf, int len)
{
rc4030_dma s = dma;
- rc4030_do_dma(s->opaque, s->n, buf, len, 0);
+ rc4030_do_dma(s->opaque, s->n, buf, len, false);
}
void rc4030_dma_write(void *dma, uint8_t *buf, int len)
{
rc4030_dma s = dma;
- rc4030_do_dma(s->opaque, s->n, buf, len, 1);
+ rc4030_do_dma(s->opaque, s->n, buf, len, true);
}
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
struct rc4030DMAState *p;
int i;
- s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
- p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
+ s = (rc4030_dma *)g_new0(rc4030_dma, n);
+ p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
for (i = 0; i < n; i++) {
p->opaque = opaque;
p->n = i;
s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
rc4030_periodic_timer, s);
- memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
+ memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s,
"rc4030.chipset", 0x300);
- memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
+ memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s,
"rc4030.jazzio", 0x00001000);
- memory_region_init_iommu(&s->dma_mr, o, &rc4030_dma_ops,
- "rc4030.dma", UINT32_MAX);
- address_space_init(&s->dma_as, &s->dma_mr, "rc4030-dma");
+ memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
+ TYPE_RC4030_IOMMU_MEMORY_REGION,
+ o, "rc4030.dma", 4 * GiB);
+ address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");
}
-static void rc4030_unrealize(DeviceState *dev, Error **errp)
+static void rc4030_unrealize(DeviceState *dev)
{
rc4030State *s = RC4030(dev);
.class_init = rc4030_class_init,
};
+static void rc4030_iommu_memory_region_class_init(ObjectClass *klass,
+ void *data)
+{
+ IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass);
+
+ imrc->translate = rc4030_dma_translate;
+}
+
+static const TypeInfo rc4030_iommu_memory_region_info = {
+ .parent = TYPE_IOMMU_MEMORY_REGION,
+ .name = TYPE_RC4030_IOMMU_MEMORY_REGION,
+ .class_init = rc4030_iommu_memory_region_class_init,
+};
+
static void rc4030_register_types(void)
{
type_register_static(&rc4030_info);
+ type_register_static(&rc4030_iommu_memory_region_info);
}
type_init(rc4030_register_types)
-DeviceState *rc4030_init(rc4030_dma **dmas, MemoryRegion **dma_mr)
+DeviceState *rc4030_init(rc4030_dma **dmas, IOMMUMemoryRegion **dma_mr)
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_RC4030);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_RC4030);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
*dmas = rc4030_allocate_dmas(dev, 4);
*dma_mr = &RC4030(dev)->dma_mr;
projects / mirror_qemu.git / blobdiff