#include "hw/mips/mips.h"
#include "hw/sysbus.h"
#include "migration/vmstate.h"
+#include "qapi/error.h"
#include "qemu/timer.h"
#include "qemu/log.h"
#include "qemu/module.h"
#include "exec/address-spaces.h"
#include "trace.h"
+#include "qom/object.h"
/********************************************************/
/* rc4030 emulation */
#define DMA_FLAG_ADDR_INTR 0x0400
#define TYPE_RC4030 "rc4030"
-#define RC4030(obj) \
- OBJECT_CHECK(rc4030State, (obj), TYPE_RC4030)
+OBJECT_DECLARE_SIMPLE_TYPE(rc4030State, RC4030)
#define TYPE_RC4030_IOMMU_MEMORY_REGION "rc4030-iommu-memory-region"
-typedef struct rc4030State {
+struct rc4030State {
SysBusDevice parent;
MemoryRegion iomem_chipset;
MemoryRegion iomem_jazzio;
-} rc4030State;
+};
static void set_next_tick(rc4030State *s)
{
pending = s->isr_jazz & s->imr_jazz;
- if (pending != 0)
+ if (pending != 0) {
qemu_irq_raise(s->jazz_bus_irq);
- else
+ } else {
qemu_irq_lower(s->jazz_bus_irq);
+ }
}
static void rc4030_irq_jazz_request(void *opaque, int irq, int level)
if (i < s->dma_tl_limit / sizeof(entry)) {
entry_address = (s->dma_tl_base & 0x7fffffff) + i * sizeof(entry);
if (address_space_read(ret.target_as, entry_address,
- MEMTXATTRS_UNSPECIFIED, (unsigned char *)&entry,
- sizeof(entry)) == MEMTX_OK) {
+ MEMTXATTRS_UNSPECIFIED, &entry, sizeof(entry))
+ == MEMTX_OK) {
ret.translated_addr = entry.frame & ~(DMA_PAGESIZE - 1);
ret.perm = IOMMU_RW;
}
}
};
-static void rc4030_do_dma(void *opaque, int n, uint8_t *buf, int len, int is_write)
+static void rc4030_do_dma(void *opaque, int n, uint8_t *buf,
+ int len, bool is_write)
{
rc4030State *s = opaque;
hwaddr dma_addr;
void rc4030_dma_read(void *dma, uint8_t *buf, int len)
{
rc4030_dma s = dma;
- rc4030_do_dma(s->opaque, s->n, buf, len, 0);
+ rc4030_do_dma(s->opaque, s->n, buf, len, false);
}
void rc4030_dma_write(void *dma, uint8_t *buf, int len)
{
rc4030_dma s = dma;
- rc4030_do_dma(s->opaque, s->n, buf, len, 1);
+ rc4030_do_dma(s->opaque, s->n, buf, len, true);
}
static rc4030_dma *rc4030_allocate_dmas(void *opaque, int n)
struct rc4030DMAState *p;
int i;
- s = (rc4030_dma *)g_malloc0(sizeof(rc4030_dma) * n);
- p = (struct rc4030DMAState *)g_malloc0(sizeof(struct rc4030DMAState) * n);
+ s = (rc4030_dma *)g_new0(rc4030_dma, n);
+ p = (struct rc4030DMAState *)g_new0(struct rc4030DMAState, n);
for (i = 0; i < n; i++) {
p->opaque = opaque;
p->n = i;
s->periodic_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
rc4030_periodic_timer, s);
- memory_region_init_io(&s->iomem_chipset, NULL, &rc4030_ops, s,
+ memory_region_init_io(&s->iomem_chipset, o, &rc4030_ops, s,
"rc4030.chipset", 0x300);
- memory_region_init_io(&s->iomem_jazzio, NULL, &jazzio_ops, s,
+ memory_region_init_io(&s->iomem_jazzio, o, &jazzio_ops, s,
"rc4030.jazzio", 0x00001000);
memory_region_init_iommu(&s->dma_mr, sizeof(s->dma_mr),
address_space_init(&s->dma_as, MEMORY_REGION(&s->dma_mr), "rc4030-dma");
}
-static void rc4030_unrealize(DeviceState *dev, Error **errp)
+static void rc4030_unrealize(DeviceState *dev)
{
rc4030State *s = RC4030(dev);
{
DeviceState *dev;
- dev = qdev_create(NULL, TYPE_RC4030);
- qdev_init_nofail(dev);
+ dev = qdev_new(TYPE_RC4030);
+ sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
*dmas = rc4030_allocate_dmas(dev, 4);
*dma_mr = &RC4030(dev)->dma_mr;