* THE SOFTWARE.
*/
-#include <stdio.h>
-#include <ctype.h>
-#include "hw.h"
+#include "sysbus.h"
#include "qemu-char.h"
-#include "etraxfs.h"
#define D(x)
-#define RW_TR_CTRL 0x00
-#define RW_TR_DMA_EN 0x04
-#define RW_REC_CTRL 0x08
-#define RW_DOUT 0x1c
-#define RS_STAT_DIN 0x20
-#define R_STAT_DIN 0x24
-#define RW_INTR_MASK 0x2c
-#define RW_ACK_INTR 0x30
-#define R_INTR 0x34
-#define R_MASKED_INTR 0x38
+#define RW_TR_CTRL (0x00 / 4)
+#define RW_TR_DMA_EN (0x04 / 4)
+#define RW_REC_CTRL (0x08 / 4)
+#define RW_DOUT (0x1c / 4)
+#define RS_STAT_DIN (0x20 / 4)
+#define R_STAT_DIN (0x24 / 4)
+#define RW_INTR_MASK (0x2c / 4)
+#define RW_ACK_INTR (0x30 / 4)
+#define R_INTR (0x34 / 4)
+#define R_MASKED_INTR (0x38 / 4)
+#define R_MAX (0x3c / 4)
#define STAT_DAV 16
#define STAT_TR_IDLE 22
#define STAT_TR_RDY 24
-struct etrax_serial_t
+struct etrax_serial
{
- CPUState *env;
- CharDriverState *chr;
- qemu_irq *irq;
-
- int pending_tx;
-
- /* Control registers. */
- uint32_t rw_tr_ctrl;
- uint32_t rw_tr_dma_en;
- uint32_t rw_rec_ctrl;
- uint32_t rs_stat_din;
- uint32_t r_stat_din;
- uint32_t rw_intr_mask;
- uint32_t rw_ack_intr;
- uint32_t r_intr;
- uint32_t r_masked_intr;
+ SysBusDevice busdev;
+ CharDriverState *chr;
+ qemu_irq irq;
+
+ int pending_tx;
+
+ uint8_t rx_fifo[16];
+ unsigned int rx_fifo_pos;
+ unsigned int rx_fifo_len;
+
+ /* Control registers. */
+ uint32_t regs[R_MAX];
};
-static void ser_update_irq(struct etrax_serial_t *s)
+static void ser_update_irq(struct etrax_serial *s)
{
- s->r_intr &= ~(s->rw_ack_intr);
- s->r_masked_intr = s->r_intr & s->rw_intr_mask;
-
- D(printf("irq_mask=%x r_intr=%x rmi=%x airq=%x \n",
- s->rw_intr_mask, s->r_intr,
- s->r_masked_intr, s->rw_ack_intr));
- qemu_set_irq(s->irq[0], !!s->r_masked_intr);
- s->rw_ack_intr = 0;
+
+ if (s->rx_fifo_len) {
+ s->regs[R_INTR] |= 8;
+ } else {
+ s->regs[R_INTR] &= ~8;
+ }
+
+ s->regs[R_MASKED_INTR] = s->regs[R_INTR] & s->regs[RW_INTR_MASK];
+ qemu_set_irq(s->irq, !!s->regs[R_MASKED_INTR]);
}
static uint32_t ser_readl (void *opaque, target_phys_addr_t addr)
{
- struct etrax_serial_t *s = opaque;
- D(CPUState *env = s->env);
- uint32_t r = 0;
-
- switch (addr)
- {
- case RW_TR_CTRL:
- r = s->rw_tr_ctrl;
- break;
- case RW_TR_DMA_EN:
- r = s->rw_tr_dma_en;
- break;
- case RS_STAT_DIN:
- r = s->rs_stat_din;
- /* clear dav. */
- s->rs_stat_din &= ~(1 << STAT_DAV);
- break;
- case R_STAT_DIN:
- r = s->rs_stat_din;
- break;
- case RW_ACK_INTR:
- D(printf("load rw_ack_intr=%x\n", s->rw_ack_intr));
- r = s->rw_ack_intr;
- break;
- case RW_INTR_MASK:
- r = s->rw_intr_mask;
- break;
- case R_INTR:
- D(printf("load r_intr=%x\n", s->r_intr));
- r = s->r_intr;
- break;
- case R_MASKED_INTR:
- D(printf("load r_maked_intr=%x\n", s->r_masked_intr));
- r = s->r_masked_intr;
- break;
-
- default:
- D(printf ("%s %x\n", __func__, addr));
- break;
- }
- return r;
+ struct etrax_serial *s = opaque;
+ D(CPUState *env = s->env);
+ uint32_t r = 0;
+
+ addr >>= 2;
+ switch (addr)
+ {
+ case R_STAT_DIN:
+ r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
+ if (s->rx_fifo_len) {
+ r |= 1 << STAT_DAV;
+ }
+ r |= 1 << STAT_TR_RDY;
+ r |= 1 << STAT_TR_IDLE;
+ break;
+ case RS_STAT_DIN:
+ r = s->rx_fifo[(s->rx_fifo_pos - s->rx_fifo_len) & 15];
+ if (s->rx_fifo_len) {
+ r |= 1 << STAT_DAV;
+ s->rx_fifo_len--;
+ }
+ r |= 1 << STAT_TR_RDY;
+ r |= 1 << STAT_TR_IDLE;
+ break;
+ default:
+ r = s->regs[addr];
+ D(printf ("%s " TARGET_FMT_plx "=%x\n", __func__, addr, r));
+ break;
+ }
+ return r;
}
static void
ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- struct etrax_serial_t *s = opaque;
- unsigned char ch = value;
- D(CPUState *env = s->env);
-
- switch (addr)
- {
- case RW_TR_CTRL:
- D(printf("rw_tr_ctrl=%x\n", value));
- s->rw_tr_ctrl = value;
- break;
- case RW_TR_DMA_EN:
- D(printf("rw_tr_dma_en=%x\n", value));
- s->rw_tr_dma_en = value;
- break;
- case RW_DOUT:
- qemu_chr_write(s->chr, &ch, 1);
- s->r_intr |= 1;
- s->pending_tx = 1;
- break;
- case RW_ACK_INTR:
- D(printf("rw_ack_intr=%x\n", value));
- s->rw_ack_intr = value;
- if (s->pending_tx && (s->rw_ack_intr & 1)) {
- s->r_intr |= 1;
- s->pending_tx = 0;
- s->rw_ack_intr &= ~1;
- }
- break;
- case RW_INTR_MASK:
- D(printf("r_intr_mask=%x\n", value));
- s->rw_intr_mask = value;
- break;
- default:
- D(printf ("%s %x %x\n", __func__, addr, value));
- break;
- }
- ser_update_irq(s);
+ struct etrax_serial *s = opaque;
+ unsigned char ch = value;
+ D(CPUState *env = s->env);
+
+ D(printf ("%s " TARGET_FMT_plx "=%x\n", __func__, addr, value));
+ addr >>= 2;
+ switch (addr)
+ {
+ case RW_DOUT:
+ qemu_chr_write(s->chr, &ch, 1);
+ s->regs[R_INTR] |= 3;
+ s->pending_tx = 1;
+ s->regs[addr] = value;
+ break;
+ case RW_ACK_INTR:
+ if (s->pending_tx) {
+ value &= ~1;
+ s->pending_tx = 0;
+ D(printf("fixedup value=%x r_intr=%x\n", value, s->regs[R_INTR]));
+ }
+ s->regs[addr] = value;
+ s->regs[R_INTR] &= ~value;
+ D(printf("r_intr=%x\n", s->regs[R_INTR]));
+ break;
+ default:
+ s->regs[addr] = value;
+ break;
+ }
+ ser_update_irq(s);
}
-static CPUReadMemoryFunc *ser_read[] = {
- NULL, NULL,
- &ser_readl,
+static CPUReadMemoryFunc * const ser_read[] = {
+ NULL, NULL,
+ &ser_readl,
};
-static CPUWriteMemoryFunc *ser_write[] = {
- NULL, NULL,
- &ser_writel,
+static CPUWriteMemoryFunc * const ser_write[] = {
+ NULL, NULL,
+ &ser_writel,
};
static void serial_receive(void *opaque, const uint8_t *buf, int size)
{
- struct etrax_serial_t *s = opaque;
-
- s->r_intr |= 8;
- s->rs_stat_din &= ~0xff;
- s->rs_stat_din |= (buf[0] & 0xff);
- s->rs_stat_din |= (1 << STAT_DAV); /* dav. */
- ser_update_irq(s);
+ struct etrax_serial *s = opaque;
+ int i;
+
+ /* Got a byte. */
+ if (s->rx_fifo_len >= 16) {
+ printf("WARNING: UART dropped char.\n");
+ return;
+ }
+
+ for (i = 0; i < size; i++) {
+ s->rx_fifo[s->rx_fifo_pos] = buf[i];
+ s->rx_fifo_pos++;
+ s->rx_fifo_pos &= 15;
+ s->rx_fifo_len++;
+ }
+
+ ser_update_irq(s);
}
static int serial_can_receive(void *opaque)
{
- struct etrax_serial_t *s = opaque;
- int r;
+ struct etrax_serial *s = opaque;
+ int r;
- /* Is the receiver enabled? */
- r = s->rw_rec_ctrl & 1;
+ /* Is the receiver enabled? */
+ if (!(s->regs[RW_REC_CTRL] & (1 << 3))) {
+ return 0;
+ }
- /* Pending rx data? */
- r |= !(s->r_intr & 8);
- return r;
+ r = sizeof(s->rx_fifo) - s->rx_fifo_len;
+ return r;
}
static void serial_event(void *opaque, int event)
}
-void etraxfs_ser_init(CPUState *env, qemu_irq *irq, CharDriverState *chr,
- target_phys_addr_t base)
+static int etraxfs_ser_init(SysBusDevice *dev)
{
- struct etrax_serial_t *s;
- int ser_regs;
-
- s = qemu_mallocz(sizeof *s);
-
- s->env = env;
- s->irq = irq;
- s->chr = chr;
-
- /* transmitter begins ready and idle. */
- s->rs_stat_din |= (1 << STAT_TR_RDY);
- s->rs_stat_din |= (1 << STAT_TR_IDLE);
-
- qemu_chr_add_handlers(chr, serial_can_receive, serial_receive,
- serial_event, s);
+ struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
+ int ser_regs;
+
+ /* transmitter begins ready and idle. */
+ s->regs[RS_STAT_DIN] |= (1 << STAT_TR_RDY);
+ s->regs[RS_STAT_DIN] |= (1 << STAT_TR_IDLE);
+
+ sysbus_init_irq(dev, &s->irq);
+ ser_regs = cpu_register_io_memory(ser_read, ser_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, R_MAX * 4, ser_regs);
+ s->chr = qdev_init_chardev(&dev->qdev);
+ if (s->chr)
+ qemu_chr_add_handlers(s->chr,
+ serial_can_receive, serial_receive,
+ serial_event, s);
+ return 0;
+}
- ser_regs = cpu_register_io_memory(0, ser_read, ser_write, s);
- cpu_register_physical_memory (base, 0x3c, ser_regs);
+static void etraxfs_serial_register(void)
+{
+ sysbus_register_dev("etraxfs,serial", sizeof (struct etrax_serial),
+ etraxfs_ser_init);
}
+
+device_init(etraxfs_serial_register)
projects / qemu.git / blobdiff