/*
- * QEMU Grackle (heathrow PPC) PCI host
+ * QEMU Grackle PCI host (heathrow OldWorld PowerMac)
+ *
+ * Copyright (c) 2006-2007 Fabrice Bellard
+ * Copyright (c) 2007 Jocelyn Mayer
*
- * Copyright (c) 2006 Fabrice Bellard
- *
* Permission is hereby granted, free of charge, to any person obtaining a copy
* of this software and associated documentation files (the "Software"), to deal
* in the Software without restriction, including without limitation the rights
* THE SOFTWARE.
*/
-#include "vl.h"
-typedef target_phys_addr_t pci_addr_t;
+#include "sysbus.h"
+#include "ppc_mac.h"
+#include "pci.h"
#include "pci_host.h"
-typedef PCIHostState GrackleState;
+/* debug Grackle */
+//#define DEBUG_GRACKLE
-static void pci_grackle_config_writel (void *opaque, target_phys_addr_t addr,
- uint32_t val)
-{
- GrackleState *s = opaque;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
+#ifdef DEBUG_GRACKLE
+#define GRACKLE_DPRINTF(fmt, ...) \
+ do { printf("GRACKLE: " fmt , ## __VA_ARGS__); } while (0)
+#else
+#define GRACKLE_DPRINTF(fmt, ...)
#endif
- s->config_reg = val;
+
+typedef struct GrackleState {
+ SysBusDevice busdev;
+ PCIHostState host_state;
+} GrackleState;
+
+/* Don't know if this matches real hardware, but it agrees with OHW. */
+static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
+{
+ return (irq_num + (pci_dev->devfn >> 3)) & 3;
}
-static uint32_t pci_grackle_config_readl (void *opaque, target_phys_addr_t addr)
+static void pci_grackle_set_irq(void *opaque, int irq_num, int level)
{
- GrackleState *s = opaque;
- uint32_t val;
+ qemu_irq *pic = opaque;
- val = s->config_reg;
-#ifdef TARGET_WORDS_BIGENDIAN
- val = bswap32(val);
-#endif
- return val;
+ GRACKLE_DPRINTF("set_irq num %d level %d\n", irq_num, level);
+ qemu_set_irq(pic[irq_num + 0x15], level);
}
-static CPUWriteMemoryFunc *pci_grackle_config_write[] = {
- &pci_grackle_config_writel,
- &pci_grackle_config_writel,
- &pci_grackle_config_writel,
-};
+static void pci_grackle_reset(void *opaque)
+{
+}
-static CPUReadMemoryFunc *pci_grackle_config_read[] = {
- &pci_grackle_config_readl,
- &pci_grackle_config_readl,
- &pci_grackle_config_readl,
-};
+PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic)
+{
+ DeviceState *dev;
+ SysBusDevice *s;
+ GrackleState *d;
-static CPUWriteMemoryFunc *pci_grackle_write[] = {
- &pci_host_data_writeb,
- &pci_host_data_writew,
- &pci_host_data_writel,
-};
+ dev = qdev_create(NULL, "grackle");
+ qdev_init_nofail(dev);
+ s = sysbus_from_qdev(dev);
+ d = FROM_SYSBUS(GrackleState, s);
+ d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci",
+ pci_grackle_set_irq,
+ pci_grackle_map_irq,
+ pic, 0, 4);
-static CPUReadMemoryFunc *pci_grackle_read[] = {
- &pci_host_data_readb,
- &pci_host_data_readw,
- &pci_host_data_readl,
-};
+ pci_create_simple(d->host_state.bus, 0, "grackle");
-/* Don't know if this matches real hardware, but it agrees with OHW. */
-static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num)
-{
- return (irq_num + (pci_dev->devfn >> 3)) & 3;
-}
+ sysbus_mmio_map(s, 0, base);
+ sysbus_mmio_map(s, 1, base + 0x00200000);
-static void pci_grackle_set_irq(void *pic, int irq_num, int level)
-{
- heathrow_pic_set_irq(pic, irq_num + 8, level);
+ return d->host_state.bus;
}
-PCIBus *pci_grackle_init(uint32_t base, void *pic)
+static int pci_grackle_init_device(SysBusDevice *dev)
{
GrackleState *s;
- PCIDevice *d;
int pci_mem_config, pci_mem_data;
- s = qemu_mallocz(sizeof(GrackleState));
- s->bus = pci_register_bus(pci_grackle_set_irq, pci_grackle_map_irq, pic, 0);
-
- pci_mem_config = cpu_register_io_memory(0, pci_grackle_config_read,
- pci_grackle_config_write, s);
- pci_mem_data = cpu_register_io_memory(0, pci_grackle_read,
- pci_grackle_write, s);
- cpu_register_physical_memory(base, 0x1000, pci_mem_config);
- cpu_register_physical_memory(base + 0x00200000, 0x1000, pci_mem_data);
- d = pci_register_device(s->bus, "Grackle host bridge", sizeof(PCIDevice),
- 0, NULL, NULL);
- d->config[0x00] = 0x57; // vendor_id
- d->config[0x01] = 0x10;
- d->config[0x02] = 0x02; // device_id
- d->config[0x03] = 0x00;
- d->config[0x08] = 0x00; // revision
+ s = FROM_SYSBUS(GrackleState, dev);
+
+ pci_mem_config = pci_host_conf_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ pci_mem_data = pci_host_data_register_mmio(&s->host_state,
+ DEVICE_LITTLE_ENDIAN);
+ sysbus_init_mmio(dev, 0x1000, pci_mem_config);
+ sysbus_init_mmio(dev, 0x1000, pci_mem_data);
+
+ qemu_register_reset(pci_grackle_reset, &s->host_state);
+ return 0;
+}
+
+static int grackle_pci_host_init(PCIDevice *d)
+{
d->config[0x09] = 0x01;
- d->config[0x0a] = 0x00; // class_sub = host
- d->config[0x0b] = 0x06; // class_base = PCI_bridge
- d->config[0x0e] = 0x00; // header_type
-
- d->config[0x18] = 0x00; // primary_bus
- d->config[0x19] = 0x01; // secondary_bus
- d->config[0x1a] = 0x00; // subordinate_bus
- d->config[0x1c] = 0x00;
- d->config[0x1d] = 0x00;
-
- d->config[0x20] = 0x00; // memory_base
- d->config[0x21] = 0x00;
- d->config[0x22] = 0x01; // memory_limit
- d->config[0x23] = 0x00;
-
- d->config[0x24] = 0x00; // prefetchable_memory_base
- d->config[0x25] = 0x00;
- d->config[0x26] = 0x00; // prefetchable_memory_limit
- d->config[0x27] = 0x00;
-
-#if 0
- /* PCI2PCI bridge same values as PearPC - check this */
- d->config[0x00] = 0x11; // vendor_id
- d->config[0x01] = 0x10;
- d->config[0x02] = 0x26; // device_id
- d->config[0x03] = 0x00;
- d->config[0x08] = 0x02; // revision
- d->config[0x0a] = 0x04; // class_sub = pci2pci
- d->config[0x0b] = 0x06; // class_base = PCI_bridge
- d->config[0x0e] = 0x01; // header_type
-
- d->config[0x18] = 0x0; // primary_bus
- d->config[0x19] = 0x1; // secondary_bus
- d->config[0x1a] = 0x1; // subordinate_bus
- d->config[0x1c] = 0x10; // io_base
- d->config[0x1d] = 0x20; // io_limit
-
- d->config[0x20] = 0x80; // memory_base
- d->config[0x21] = 0x80;
- d->config[0x22] = 0x90; // memory_limit
- d->config[0x23] = 0x80;
-
- d->config[0x24] = 0x00; // prefetchable_memory_base
- d->config[0x25] = 0x84;
- d->config[0x26] = 0x00; // prefetchable_memory_limit
- d->config[0x27] = 0x85;
-#endif
- return s->bus;
+ return 0;
+}
+
+static PCIDeviceInfo grackle_pci_host_info = {
+ .qdev.name = "grackle",
+ .qdev.size = sizeof(PCIDevice),
+ .init = grackle_pci_host_init,
+ .vendor_id = PCI_VENDOR_ID_MOTOROLA,
+ .device_id = PCI_DEVICE_ID_MOTOROLA_MPC106,
+ .revision = 0x00,
+ .class_id = PCI_CLASS_BRIDGE_HOST,
+};
+
+static void grackle_register_devices(void)
+{
+ sysbus_register_dev("grackle", sizeof(GrackleState),
+ pci_grackle_init_device);
+ pci_qdev_register(&grackle_pci_host_info);
}
+device_init(grackle_register_devices)
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