#include <hw/mac_dbdma.h>
#include "block.h"
#include "block_int.h"
-#include "sysemu.h"
#include "dma.h"
#include <hw/ide/internal.h>
BlockDriverAIOCB *aiocb;
} MACIOIDEState;
+#define MACIO_PAGE_SIZE 4096
+
static void pmac_ide_atapi_transfer_cb(void *opaque, int ret)
{
DBDMA_io *io = opaque;
s->io_buffer_size = io->len;
- qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
+ qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
qemu_sglist_add(&s->sg, io->addr, io->len);
io->addr += io->len;
io->len = 0;
s->io_buffer_index = 0;
s->io_buffer_size = io->len;
- qemu_sglist_init(&s->sg, io->len / TARGET_PAGE_SIZE + 1);
+ qemu_sglist_init(&s->sg, io->len / MACIO_PAGE_SIZE + 1);
qemu_sglist_add(&s->sg, io->addr, io->len);
io->addr += io->len;
io->len = 0;
IDEState *s = idebus_active_if(&m->bus);
s->io_buffer_size = 0;
- if (s->is_cdrom) {
+ if (s->drive_kind == IDE_CD) {
pmac_ide_atapi_transfer_cb(io, 0);
return;
}
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
-#ifdef TARGET_WORDS_BIGENDIAN
val = bswap16(val);
-#endif
if (addr == 0) {
ide_data_writew(&d->bus, 0, val);
}
} else {
retval = 0xFFFF;
}
-#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap16(retval);
-#endif
return retval;
}
MACIOIDEState *d = opaque;
addr = (addr & 0xFFF) >> 4;
-#ifdef TARGET_WORDS_BIGENDIAN
val = bswap32(val);
-#endif
if (addr == 0) {
ide_data_writel(&d->bus, 0, val);
}
} else {
retval = 0xFFFFFFFF;
}
-#ifdef TARGET_WORDS_BIGENDIAN
retval = bswap32(retval);
-#endif
return retval;
}
{
MACIOIDEState *d = opaque;
- ide_reset(d->bus.ifs +0);
- ide_reset(d->bus.ifs +1);
+ ide_bus_reset(&d->bus);
}
/* hd_table must contain 4 block drivers */
int pmac_ide_memory;
d = qemu_mallocz(sizeof(MACIOIDEState));
- ide_init2(&d->bus, hd_table[0], hd_table[1], irq);
+ ide_init2_with_non_qdev_drives(&d->bus, hd_table[0], hd_table[1], irq);
if (dbdma)
DBDMA_register_channel(dbdma, channel, dma_irq, pmac_ide_transfer, pmac_ide_flush, d);
pmac_ide_memory = cpu_register_io_memory(pmac_ide_read,
- pmac_ide_write, d);
- vmstate_register(0, &vmstate_pmac, d);
+ pmac_ide_write, d,
+ DEVICE_NATIVE_ENDIAN);
+ vmstate_register(NULL, 0, &vmstate_pmac, d);
qemu_register_reset(pmac_ide_reset, d);
- pmac_ide_reset(d);
return pmac_ide_memory;
}