* This code is licenced under the GPL
*/
-#include "hw.h"
+#include "sysbus.h"
#include "primecell.h"
#include "devices.h"
-#include "sysemu.h"
#include "boards.h"
#include "arm-misc.h"
#include "net.h"
typedef struct {
+ SysBusDevice busdev;
+ uint32_t memsz;
uint32_t flash_offset;
uint32_t cm_osc;
uint32_t cm_ctrl;
}
case 6: /* CM_LMBUSCNT */
/* ??? High frequency timer. */
- cpu_abort(cpu_single_env, "integratorcm_read: CM_LMBUSCNT");
+ hw_error("integratorcm_read: CM_LMBUSCNT");
case 7: /* CM_AUXOSC */
return s->cm_auxosc;
case 8: /* CM_SDRAM */
return s->cm_init;
case 10: /* CM_REFCT */
/* ??? High frequency timer. */
- cpu_abort(cpu_single_env, "integratorcm_read: CM_REFCT");
+ hw_error("integratorcm_read: CM_REFCT");
case 12: /* CM_FLAGS */
return s->cm_flags;
case 14: /* CM_NVFLAGS */
/* ??? Voltage control unimplemented. */
return 0;
default:
- cpu_abort (cpu_single_env,
- "integratorcm_read: Unimplemented offset 0x%x\n", (int)offset);
+ hw_error("integratorcm_read: Unimplemented offset 0x%x\n",
+ (int)offset);
return 0;
}
}
static void integratorcm_set_ctrl(integratorcm_state *s, uint32_t value)
{
if (value & 8) {
- cpu_abort(cpu_single_env, "Board reset\n");
+ hw_error("Board reset\n");
}
if ((s->cm_init ^ value) & 4) {
integratorcm_do_remap(s, (value & 4) == 0);
/* ??? The CPU irq/fiq is raised when either the core module or base PIC
are active. */
if (s->int_level & (s->irq_enabled | s->fiq_enabled))
- cpu_abort(cpu_single_env, "Core module interrupt\n");
+ hw_error("Core module interrupt\n");
}
static void integratorcm_write(void *opaque, target_phys_addr_t offset,
/* ??? Voltage control unimplemented. */
break;
default:
- cpu_abort (cpu_single_env,
- "integratorcm_write: Unimplemented offset 0x%x\n", (int)offset);
+ hw_error("integratorcm_write: Unimplemented offset 0x%x\n",
+ (int)offset);
break;
}
}
/* Integrator/CM control registers. */
-static CPUReadMemoryFunc *integratorcm_readfn[] = {
+static CPUReadMemoryFunc * const integratorcm_readfn[] = {
integratorcm_read,
integratorcm_read,
integratorcm_read
};
-static CPUWriteMemoryFunc *integratorcm_writefn[] = {
+static CPUWriteMemoryFunc * const integratorcm_writefn[] = {
integratorcm_write,
integratorcm_write,
integratorcm_write
};
-static void integratorcm_init(int memsz)
+static int integratorcm_init(SysBusDevice *dev)
{
int iomemtype;
- integratorcm_state *s;
+ integratorcm_state *s = FROM_SYSBUS(integratorcm_state, dev);
- s = (integratorcm_state *)qemu_mallocz(sizeof(integratorcm_state));
s->cm_osc = 0x01000048;
/* ??? What should the high bits of this value be? */
s->cm_auxosc = 0x0007feff;
s->cm_sdram = 0x00011122;
- if (memsz >= 256) {
+ if (s->memsz >= 256) {
integrator_spd[31] = 64;
s->cm_sdram |= 0x10;
- } else if (memsz >= 128) {
+ } else if (s->memsz >= 128) {
integrator_spd[31] = 32;
s->cm_sdram |= 0x0c;
- } else if (memsz >= 64) {
+ } else if (s->memsz >= 64) {
integrator_spd[31] = 16;
s->cm_sdram |= 0x08;
- } else if (memsz >= 32) {
+ } else if (s->memsz >= 32) {
integrator_spd[31] = 4;
s->cm_sdram |= 0x04;
} else {
}
memcpy(integrator_spd + 73, "QEMU-MEMORY", 11);
s->cm_init = 0x00000112;
- s->flash_offset = qemu_ram_alloc(0x100000);
+ s->flash_offset = qemu_ram_alloc(NULL, "integrator.flash", 0x100000);
- iomemtype = cpu_register_io_memory(0, integratorcm_readfn,
- integratorcm_writefn, s);
- cpu_register_physical_memory(0x10000000, 0x00800000, iomemtype);
+ iomemtype = cpu_register_io_memory(integratorcm_readfn,
+ integratorcm_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, 0x00800000, iomemtype);
integratorcm_do_remap(s, 1);
/* ??? Save/restore. */
+ return 0;
}
/* Integrator/CP hardware emulation. */
typedef struct icp_pic_state
{
+ SysBusDevice busdev;
uint32_t level;
uint32_t irq_enabled;
uint32_t fiq_enabled;
icp_pic_update(s);
}
-static CPUReadMemoryFunc *icp_pic_readfn[] = {
+static CPUReadMemoryFunc * const icp_pic_readfn[] = {
icp_pic_read,
icp_pic_read,
icp_pic_read
};
-static CPUWriteMemoryFunc *icp_pic_writefn[] = {
+static CPUWriteMemoryFunc * const icp_pic_writefn[] = {
icp_pic_write,
icp_pic_write,
icp_pic_write
};
-static qemu_irq *icp_pic_init(uint32_t base,
- qemu_irq parent_irq, qemu_irq parent_fiq)
+static int icp_pic_init(SysBusDevice *dev)
{
- icp_pic_state *s;
+ icp_pic_state *s = FROM_SYSBUS(icp_pic_state, dev);
int iomemtype;
- qemu_irq *qi;
-
- s = (icp_pic_state *)qemu_mallocz(sizeof(icp_pic_state));
- qi = qemu_allocate_irqs(icp_pic_set_irq, s, 32);
- s->parent_irq = parent_irq;
- s->parent_fiq = parent_fiq;
- iomemtype = cpu_register_io_memory(0, icp_pic_readfn,
- icp_pic_writefn, s);
- cpu_register_physical_memory(base, 0x00800000, iomemtype);
- /* ??? Save/restore. */
- return qi;
+
+ qdev_init_gpio_in(&dev->qdev, icp_pic_set_irq, 32);
+ sysbus_init_irq(dev, &s->parent_irq);
+ sysbus_init_irq(dev, &s->parent_fiq);
+ iomemtype = cpu_register_io_memory(icp_pic_readfn,
+ icp_pic_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, 0x00800000, iomemtype);
+ return 0;
}
/* CP control registers. */
case 3: /* CP_DECODE */
return 0x11;
default:
- cpu_abort (cpu_single_env, "icp_control_read: Bad offset %x\n",
- (int)offset);
+ hw_error("icp_control_read: Bad offset %x\n", (int)offset);
return 0;
}
}
/* Nothing interesting implemented yet. */
break;
default:
- cpu_abort (cpu_single_env, "icp_control_write: Bad offset %x\n",
- (int)offset);
+ hw_error("icp_control_write: Bad offset %x\n", (int)offset);
}
}
-static CPUReadMemoryFunc *icp_control_readfn[] = {
+static CPUReadMemoryFunc * const icp_control_readfn[] = {
icp_control_read,
icp_control_read,
icp_control_read
};
-static CPUWriteMemoryFunc *icp_control_writefn[] = {
+static CPUWriteMemoryFunc * const icp_control_writefn[] = {
icp_control_write,
icp_control_write,
icp_control_write
{
int iomemtype;
- iomemtype = cpu_register_io_memory(0, icp_control_readfn,
- icp_control_writefn, NULL);
+ iomemtype = cpu_register_io_memory(icp_control_readfn,
+ icp_control_writefn, NULL,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(base, 0x00800000, iomemtype);
/* ??? Save/restore. */
}
.board_id = 0x113,
};
-static void integratorcp_init(ram_addr_t ram_size, int vga_ram_size,
+static void integratorcp_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename, const char *kernel_cmdline,
const char *initrd_filename, const char *cpu_model)
{
CPUState *env;
ram_addr_t ram_offset;
- qemu_irq *pic;
+ qemu_irq pic[32];
qemu_irq *cpu_pic;
- int sd;
+ DeviceState *dev;
+ int i;
if (!cpu_model)
cpu_model = "arm926";
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- ram_offset = qemu_ram_alloc(ram_size);
+ ram_offset = qemu_ram_alloc(NULL, "integrator.ram", ram_size);
/* ??? On a real system the first 1Mb is mapped as SSRAM or boot flash. */
/* ??? RAM should repeat to fill physical memory space. */
/* SDRAM at address zero*/
/* And again at address 0x80000000 */
cpu_register_physical_memory(0x80000000, ram_size, ram_offset | IO_MEM_RAM);
- integratorcm_init(ram_size >> 20);
+ dev = qdev_create(NULL, "integrator_core");
+ qdev_prop_set_uint32(dev, "memsz", ram_size >> 20);
+ qdev_init_nofail(dev);
+ sysbus_mmio_map((SysBusDevice *)dev, 0, 0x10000000);
+
cpu_pic = arm_pic_init_cpu(env);
- pic = icp_pic_init(0x14000000, cpu_pic[ARM_PIC_CPU_IRQ],
- cpu_pic[ARM_PIC_CPU_FIQ]);
- icp_pic_init(0xca000000, pic[26], NULL);
- icp_pit_init(0x13000000, pic, 5);
- pl031_init(0x15000000, pic[8]);
- pl011_init(0x16000000, pic[1], serial_hds[0], PL011_ARM);
- pl011_init(0x17000000, pic[2], serial_hds[1], PL011_ARM);
- icp_control_init(0xcb000000);
- pl050_init(0x18000000, pic[3], 0);
- pl050_init(0x19000000, pic[4], 1);
- sd = drive_get_index(IF_SD, 0, 0);
- if (sd == -1) {
- fprintf(stderr, "qemu: missing SecureDigital card\n");
- exit(1);
+ dev = sysbus_create_varargs("integrator_pic", 0x14000000,
+ cpu_pic[ARM_PIC_CPU_IRQ],
+ cpu_pic[ARM_PIC_CPU_FIQ], NULL);
+ for (i = 0; i < 32; i++) {
+ pic[i] = qdev_get_gpio_in(dev, i);
}
- pl181_init(0x1c000000, drives_table[sd].bdrv, pic[23], pic[24]);
+ sysbus_create_simple("integrator_pic", 0xca000000, pic[26]);
+ sysbus_create_varargs("integrator_pit", 0x13000000,
+ pic[5], pic[6], pic[7], NULL);
+ sysbus_create_simple("pl031", 0x15000000, pic[8]);
+ sysbus_create_simple("pl011", 0x16000000, pic[1]);
+ sysbus_create_simple("pl011", 0x17000000, pic[2]);
+ icp_control_init(0xcb000000);
+ sysbus_create_simple("pl050_keyboard", 0x18000000, pic[3]);
+ sysbus_create_simple("pl050_mouse", 0x19000000, pic[4]);
+ sysbus_create_varargs("pl181", 0x1c000000, pic[23], pic[24], NULL);
if (nd_table[0].vlan)
smc91c111_init(&nd_table[0], 0xc8000000, pic[27]);
- pl110_init(0xc0000000, pic[22], 0);
+
+ sysbus_create_simple("pl110", 0xc0000000, pic[22]);
integrator_binfo.ram_size = ram_size;
integrator_binfo.kernel_filename = kernel_filename;
arm_load_kernel(env, &integrator_binfo);
}
-QEMUMachine integratorcp_machine = {
+static QEMUMachine integratorcp_machine = {
.name = "integratorcp",
.desc = "ARM Integrator/CP (ARM926EJ-S)",
.init = integratorcp_init,
- .ram_require = 0x100000,
+ .is_default = 1,
};
+
+static void integratorcp_machine_init(void)
+{
+ qemu_register_machine(&integratorcp_machine);
+}
+
+machine_init(integratorcp_machine_init);
+
+static SysBusDeviceInfo core_info = {
+ .init = integratorcm_init,
+ .qdev.name = "integrator_core",
+ .qdev.size = sizeof(integratorcm_state),
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("memsz", integratorcm_state, memsz, 0),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void integratorcp_register_devices(void)
+{
+ sysbus_register_dev("integrator_pic", sizeof(icp_pic_state), icp_pic_init);
+ sysbus_register_withprop(&core_info);
+}
+
+device_init(integratorcp_register_devices)
projects / qemu.git / blobdiff