#include "hw/hw.h"
#include "hw/pc.h"
#include "qemu-error.h"
-#include "console.h"
+#include "ui/console.h"
#include "hw/loader.h"
-#include "monitor.h"
+#include "monitor/monitor.h"
#include "range.h"
#include "sysemu.h"
-#include "hw/pci.h"
-#include "hw/msi.h"
+#include "hw/pci/pci.h"
+#include "hw/pci/msi.h"
#include "kvm_i386.h"
#define MSIX_PAGE_SIZE 0x1000
int msi_virq_nr;
int *msi_virq;
MSIXTableEntry *msix_table;
- target_phys_addr_t msix_table_addr;
+ hwaddr msix_table_addr;
uint16_t msix_max;
MemoryRegion mmio;
char *configfd_name;
static void assigned_dev_unregister_msix_mmio(AssignedDevice *dev);
static uint64_t assigned_dev_ioport_rw(AssignedDevRegion *dev_region,
- target_phys_addr_t addr, int size,
+ hwaddr addr, int size,
uint64_t *data)
{
uint64_t val = 0;
return val;
}
-static void assigned_dev_ioport_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_ioport_write(void *opaque, hwaddr addr,
uint64_t data, unsigned size)
{
assigned_dev_ioport_rw(opaque, addr, size, &data);
}
static uint64_t assigned_dev_ioport_read(void *opaque,
- target_phys_addr_t addr, unsigned size)
+ hwaddr addr, unsigned size)
{
return assigned_dev_ioport_rw(opaque, addr, size, NULL);
}
-static uint32_t slow_bar_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readb(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint8_t *in = d->u.r_virtbase + addr;
return r;
}
-static uint32_t slow_bar_readw(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readw(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint16_t *in = (uint16_t *)(d->u.r_virtbase + addr);
return r;
}
-static uint32_t slow_bar_readl(void *opaque, target_phys_addr_t addr)
+static uint32_t slow_bar_readl(void *opaque, hwaddr addr)
{
AssignedDevRegion *d = opaque;
uint32_t *in = (uint32_t *)(d->u.r_virtbase + addr);
return r;
}
-static void slow_bar_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writeb(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint8_t *out = d->u.r_virtbase + addr;
*out = val;
}
-static void slow_bar_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writew(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint16_t *out = (uint16_t *)(d->u.r_virtbase + addr);
*out = val;
}
-static void slow_bar_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void slow_bar_writel(void *opaque, hwaddr addr, uint32_t val)
{
AssignedDevRegion *d = opaque;
uint32_t *out = (uint32_t *)(d->u.r_virtbase + addr);
intx_route = pci_device_route_intx_to_irq(&dev->dev, dev->intpin);
assert(intx_route.mode != PCI_INTX_INVERTED);
- if (dev->intx_route.mode == intx_route.mode &&
- dev->intx_route.irq == intx_route.irq) {
+ if (!pci_intx_route_changed(&dev->intx_route, &intx_route)) {
return 0;
}
}
if (ctrl_byte & PCI_MSI_FLAGS_ENABLE) {
- uint8_t *pos = pci_dev->config + pci_dev->msi_cap;
- MSIMessage msg;
+ MSIMessage msg = msi_get_message(pci_dev, 0);
int virq;
- msg.address = pci_get_long(pos + PCI_MSI_ADDRESS_LO);
- msg.data = pci_get_word(pos + PCI_MSI_DATA_32);
virq = kvm_irqchip_add_msi_route(kvm_state, msg);
if (virq < 0) {
perror("assigned_dev_update_msi: kvm_irqchip_add_msi_route");
}
static uint64_t
-assigned_dev_msix_mmio_read(void *opaque, target_phys_addr_t addr,
+assigned_dev_msix_mmio_read(void *opaque, hwaddr addr,
unsigned size)
{
AssignedDevice *adev = opaque;
return val;
}
-static void assigned_dev_msix_mmio_write(void *opaque, target_phys_addr_t addr,
+static void assigned_dev_msix_mmio_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
AssignedDevice *adev = opaque;