*/
#include "hw.h"
#include "nvram.h"
-#include "isa.h"
#include "qemu-timer.h"
#include "sysemu.h"
+#include "sysbus.h"
+#include "isa.h"
//#define DEBUG_NVRAM
* alarm and a watchdog timer and related control registers. In the
* PPC platform there is also a nvram lock function.
*/
-struct m48t59_t {
+
+/*
+ * Chipset docs:
+ * http://www.st.com/stonline/products/literature/ds/2410/m48t02.pdf
+ * http://www.st.com/stonline/products/literature/ds/2411/m48t08.pdf
+ * http://www.st.com/stonline/products/literature/od/7001/m48t59y.pdf
+ */
+
+struct M48t59State {
/* Model parameters */
- int type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
+ uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59
/* Hardware parameters */
qemu_irq IRQ;
- int mem_index;
uint32_t io_base;
- uint16_t size;
+ uint32_t size;
/* RTC management */
time_t time_offset;
time_t stop_time;
uint8_t *buffer;
};
-/* Fake timer functions */
-/* Generic helpers for BCD */
-static inline uint8_t toBCD (uint8_t value)
-{
- return (((value / 10) % 10) << 4) | (value % 10);
-}
+typedef struct M48t59ISAState {
+ ISADevice busdev;
+ M48t59State state;
+} M48t59ISAState;
-static inline uint8_t fromBCD (uint8_t BCD)
-{
- return ((BCD >> 4) * 10) + (BCD & 0x0F);
-}
+typedef struct M48t59SysBusState {
+ SysBusDevice busdev;
+ M48t59State state;
+} M48t59SysBusState;
+
+/* Fake timer functions */
/* Alarm management */
static void alarm_cb (void *opaque)
{
struct tm tm;
uint64_t next_time;
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
qemu_set_irq(NVRAM->IRQ, 1);
if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 &&
/* Repeat once a second */
next_time = 1;
}
- qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock(vm_clock) +
+ qemu_mod_timer(NVRAM->alrm_timer, qemu_get_clock_ns(vm_clock) +
next_time * 1000);
qemu_set_irq(NVRAM->IRQ, 0);
}
-static void set_alarm (m48t59_t *NVRAM)
+static void set_alarm(M48t59State *NVRAM)
{
int diff;
if (NVRAM->alrm_timer != NULL) {
}
/* RTC management helpers */
-static inline void get_time (m48t59_t *NVRAM, struct tm *tm)
+static inline void get_time(M48t59State *NVRAM, struct tm *tm)
{
qemu_get_timedate(tm, NVRAM->time_offset);
}
-static void set_time (m48t59_t *NVRAM, struct tm *tm)
+static void set_time(M48t59State *NVRAM, struct tm *tm)
{
NVRAM->time_offset = qemu_timedate_diff(tm);
set_alarm(NVRAM);
/* Watchdog management */
static void watchdog_cb (void *opaque)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->buffer[0x1FF0] |= 0x80;
if (NVRAM->buffer[0x1FF7] & 0x80) {
}
}
-static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value)
+static void set_up_watchdog(M48t59State *NVRAM, uint8_t value)
{
uint64_t interval; /* in 1/16 seconds */
/* Direct access to NVRAM */
void m48t59_write (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
int tmp;
break;
case 0x1FF2:
/* alarm seconds */
- tmp = fromBCD(val & 0x7F);
+ tmp = from_bcd(val & 0x7F);
if (tmp >= 0 && tmp <= 59) {
NVRAM->alarm.tm_sec = tmp;
NVRAM->buffer[0x1FF2] = val;
break;
case 0x1FF3:
/* alarm minutes */
- tmp = fromBCD(val & 0x7F);
+ tmp = from_bcd(val & 0x7F);
if (tmp >= 0 && tmp <= 59) {
NVRAM->alarm.tm_min = tmp;
NVRAM->buffer[0x1FF3] = val;
break;
case 0x1FF4:
/* alarm hours */
- tmp = fromBCD(val & 0x3F);
+ tmp = from_bcd(val & 0x3F);
if (tmp >= 0 && tmp <= 23) {
NVRAM->alarm.tm_hour = tmp;
NVRAM->buffer[0x1FF4] = val;
break;
case 0x1FF5:
/* alarm date */
- tmp = fromBCD(val & 0x1F);
+ tmp = from_bcd(val & 0x1F);
if (tmp != 0) {
NVRAM->alarm.tm_mday = tmp;
NVRAM->buffer[0x1FF5] = val;
case 0x1FF9:
case 0x07F9:
/* seconds (BCD) */
- tmp = fromBCD(val & 0x7F);
+ tmp = from_bcd(val & 0x7F);
if (tmp >= 0 && tmp <= 59) {
get_time(NVRAM, &tm);
tm.tm_sec = tmp;
case 0x1FFA:
case 0x07FA:
/* minutes (BCD) */
- tmp = fromBCD(val & 0x7F);
+ tmp = from_bcd(val & 0x7F);
if (tmp >= 0 && tmp <= 59) {
get_time(NVRAM, &tm);
tm.tm_min = tmp;
case 0x1FFB:
case 0x07FB:
/* hours (BCD) */
- tmp = fromBCD(val & 0x3F);
+ tmp = from_bcd(val & 0x3F);
if (tmp >= 0 && tmp <= 23) {
get_time(NVRAM, &tm);
tm.tm_hour = tmp;
case 0x1FFC:
case 0x07FC:
/* day of the week / century */
- tmp = fromBCD(val & 0x07);
+ tmp = from_bcd(val & 0x07);
get_time(NVRAM, &tm);
tm.tm_wday = tmp;
set_time(NVRAM, &tm);
case 0x1FFD:
case 0x07FD:
/* date */
- tmp = fromBCD(val & 0x1F);
+ tmp = from_bcd(val & 0x1F);
if (tmp != 0) {
get_time(NVRAM, &tm);
tm.tm_mday = tmp;
case 0x1FFE:
case 0x07FE:
/* month */
- tmp = fromBCD(val & 0x1F);
+ tmp = from_bcd(val & 0x1F);
if (tmp >= 1 && tmp <= 12) {
get_time(NVRAM, &tm);
tm.tm_mon = tmp - 1;
case 0x1FFF:
case 0x07FF:
/* year */
- tmp = fromBCD(val);
+ tmp = from_bcd(val);
if (tmp >= 0 && tmp <= 99) {
get_time(NVRAM, &tm);
if (NVRAM->type == 8)
- tm.tm_year = fromBCD(val) + 68; // Base year is 1968
+ tm.tm_year = from_bcd(val) + 68; // Base year is 1968
else
- tm.tm_year = fromBCD(val);
+ tm.tm_year = from_bcd(val);
set_time(NVRAM, &tm);
}
break;
uint32_t m48t59_read (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
struct tm tm;
uint32_t retval = 0xFF;
case 0x07F9:
/* seconds (BCD) */
get_time(NVRAM, &tm);
- retval = (NVRAM->buffer[addr] & 0x80) | toBCD(tm.tm_sec);
+ retval = (NVRAM->buffer[addr] & 0x80) | to_bcd(tm.tm_sec);
break;
case 0x1FFA:
case 0x07FA:
/* minutes (BCD) */
get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_min);
+ retval = to_bcd(tm.tm_min);
break;
case 0x1FFB:
case 0x07FB:
/* hours (BCD) */
get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_hour);
+ retval = to_bcd(tm.tm_hour);
break;
case 0x1FFC:
case 0x07FC:
case 0x07FD:
/* date */
get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_mday);
+ retval = to_bcd(tm.tm_mday);
break;
case 0x1FFE:
case 0x07FE:
/* month */
get_time(NVRAM, &tm);
- retval = toBCD(tm.tm_mon + 1);
+ retval = to_bcd(tm.tm_mon + 1);
break;
case 0x1FFF:
case 0x07FF:
/* year */
get_time(NVRAM, &tm);
if (NVRAM->type == 8)
- retval = toBCD(tm.tm_year - 68); // Base year is 1968
+ retval = to_bcd(tm.tm_year - 68); // Base year is 1968
else
- retval = toBCD(tm.tm_year);
+ retval = to_bcd(tm.tm_year);
break;
default:
/* Check lock registers state */
void m48t59_set_addr (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->addr = addr;
}
void m48t59_toggle_lock (void *opaque, int lock)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
NVRAM->lock ^= 1 << lock;
}
/* IO access to NVRAM */
static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
addr -= NVRAM->io_base;
NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val);
static uint32_t NVRAM_readb (void *opaque, uint32_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
addr -= NVRAM->io_base;
static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, value & 0xff);
}
static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 8) & 0xff);
m48t59_write(NVRAM, addr + 1, value & 0xff);
static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
m48t59_write(NVRAM, addr, (value >> 24) & 0xff);
m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff);
static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr);
static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 8;
static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr)
{
- m48t59_t *NVRAM = opaque;
+ M48t59State *NVRAM = opaque;
uint32_t retval;
retval = m48t59_read(NVRAM, addr) << 24;
return retval;
}
-static CPUWriteMemoryFunc *nvram_write[] = {
+static CPUWriteMemoryFunc * const nvram_write[] = {
&nvram_writeb,
&nvram_writew,
&nvram_writel,
};
-static CPUReadMemoryFunc *nvram_read[] = {
+static CPUReadMemoryFunc * const nvram_read[] = {
&nvram_readb,
&nvram_readw,
&nvram_readl,
};
-static void m48t59_save(QEMUFile *f, void *opaque)
+static const VMStateDescription vmstate_m48t59 = {
+ .name = "m48t59",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(lock, M48t59State),
+ VMSTATE_UINT16(addr, M48t59State),
+ VMSTATE_VBUFFER_UINT32(buffer, M48t59State, 0, NULL, 0, size),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void m48t59_reset_common(M48t59State *NVRAM)
{
- m48t59_t *s = opaque;
+ NVRAM->addr = 0;
+ NVRAM->lock = 0;
+ if (NVRAM->alrm_timer != NULL)
+ qemu_del_timer(NVRAM->alrm_timer);
- qemu_put_8s(f, &s->lock);
- qemu_put_be16s(f, &s->addr);
- qemu_put_buffer(f, s->buffer, s->size);
+ if (NVRAM->wd_timer != NULL)
+ qemu_del_timer(NVRAM->wd_timer);
}
-static int m48t59_load(QEMUFile *f, void *opaque, int version_id)
+static void m48t59_reset_isa(DeviceState *d)
{
- m48t59_t *s = opaque;
+ M48t59ISAState *isa = container_of(d, M48t59ISAState, busdev.qdev);
+ M48t59State *NVRAM = &isa->state;
- if (version_id != 1)
- return -EINVAL;
+ m48t59_reset_common(NVRAM);
+}
- qemu_get_8s(f, &s->lock);
- qemu_get_be16s(f, &s->addr);
- qemu_get_buffer(f, s->buffer, s->size);
+static void m48t59_reset_sysbus(DeviceState *d)
+{
+ M48t59SysBusState *sys = container_of(d, M48t59SysBusState, busdev.qdev);
+ M48t59State *NVRAM = &sys->state;
- return 0;
+ m48t59_reset_common(NVRAM);
}
-static void m48t59_reset(void *opaque)
+/* Initialisation routine */
+M48t59State *m48t59_init(qemu_irq IRQ, target_phys_addr_t mem_base,
+ uint32_t io_base, uint16_t size, int type)
{
- m48t59_t *NVRAM = opaque;
-
- NVRAM->addr = 0;
- NVRAM->lock = 0;
- if (NVRAM->alrm_timer != NULL)
- qemu_del_timer(NVRAM->alrm_timer);
+ DeviceState *dev;
+ SysBusDevice *s;
+ M48t59SysBusState *d;
+ M48t59State *state;
+
+ dev = qdev_create(NULL, "m48t59");
+ qdev_prop_set_uint32(dev, "type", type);
+ qdev_prop_set_uint32(dev, "size", size);
+ qdev_prop_set_uint32(dev, "io_base", io_base);
+ qdev_init_nofail(dev);
+ s = sysbus_from_qdev(dev);
+ d = FROM_SYSBUS(M48t59SysBusState, s);
+ state = &d->state;
+ sysbus_connect_irq(s, 0, IRQ);
+ if (io_base != 0) {
+ register_ioport_read(io_base, 0x04, 1, NVRAM_readb, state);
+ register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, state);
+ }
+ if (mem_base != 0) {
+ sysbus_mmio_map(s, 0, mem_base);
+ }
- if (NVRAM->wd_timer != NULL)
- qemu_del_timer(NVRAM->wd_timer);
+ return state;
}
-/* Initialisation routine */
-m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base,
- uint32_t io_base, uint16_t size,
- int type)
+M48t59State *m48t59_init_isa(uint32_t io_base, uint16_t size, int type)
{
- m48t59_t *s;
- target_phys_addr_t save_base;
-
- s = qemu_mallocz(sizeof(m48t59_t));
- s->buffer = qemu_mallocz(size);
- s->IRQ = IRQ;
- s->size = size;
- s->io_base = io_base;
- s->type = type;
+ M48t59ISAState *d;
+ ISADevice *dev;
+ M48t59State *s;
+
+ dev = isa_create("m48t59_isa");
+ qdev_prop_set_uint32(&dev->qdev, "type", type);
+ qdev_prop_set_uint32(&dev->qdev, "size", size);
+ qdev_prop_set_uint32(&dev->qdev, "io_base", io_base);
+ qdev_init_nofail(&dev->qdev);
+ d = DO_UPCAST(M48t59ISAState, busdev, dev);
+ s = &d->state;
+
if (io_base != 0) {
register_ioport_read(io_base, 0x04, 1, NVRAM_readb, s);
register_ioport_write(io_base, 0x04, 1, NVRAM_writeb, s);
+ isa_init_ioport_range(dev, io_base, 4);
}
- if (mem_base != 0) {
- s->mem_index = cpu_register_io_memory(nvram_read, nvram_write, s);
- cpu_register_physical_memory(mem_base, size, s->mem_index);
- }
- if (type == 59) {
- s->alrm_timer = qemu_new_timer(vm_clock, &alarm_cb, s);
- s->wd_timer = qemu_new_timer(vm_clock, &watchdog_cb, s);
+
+ return s;
+}
+
+static void m48t59_init_common(M48t59State *s)
+{
+ s->buffer = qemu_mallocz(s->size);
+ if (s->type == 59) {
+ s->alrm_timer = qemu_new_timer_ns(vm_clock, &alarm_cb, s);
+ s->wd_timer = qemu_new_timer_ns(vm_clock, &watchdog_cb, s);
}
qemu_get_timedate(&s->alarm, 0);
- qemu_register_reset(m48t59_reset, s);
- save_base = mem_base ? mem_base : io_base;
- register_savevm("m48t59", save_base, 1, m48t59_save, m48t59_load, s);
+ vmstate_register(NULL, -1, &vmstate_m48t59, s);
+}
- return s;
+static int m48t59_init_isa1(ISADevice *dev)
+{
+ M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev);
+ M48t59State *s = &d->state;
+
+ isa_init_irq(dev, &s->IRQ, 8);
+ m48t59_init_common(s);
+
+ return 0;
}
+
+static int m48t59_init1(SysBusDevice *dev)
+{
+ M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev);
+ M48t59State *s = &d->state;
+ int mem_index;
+
+ sysbus_init_irq(dev, &s->IRQ);
+
+ mem_index = cpu_register_io_memory(nvram_read, nvram_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, s->size, mem_index);
+ m48t59_init_common(s);
+
+ return 0;
+}
+
+static ISADeviceInfo m48t59_isa_info = {
+ .init = m48t59_init_isa1,
+ .qdev.name = "m48t59_isa",
+ .qdev.size = sizeof(M48t59ISAState),
+ .qdev.reset = m48t59_reset_isa,
+ .qdev.no_user = 1,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("size", M48t59ISAState, state.size, -1),
+ DEFINE_PROP_UINT32("type", M48t59ISAState, state.type, -1),
+ DEFINE_PROP_HEX32( "io_base", M48t59ISAState, state.io_base, 0),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static SysBusDeviceInfo m48t59_info = {
+ .init = m48t59_init1,
+ .qdev.name = "m48t59",
+ .qdev.size = sizeof(M48t59SysBusState),
+ .qdev.reset = m48t59_reset_sysbus,
+ .qdev.props = (Property[]) {
+ DEFINE_PROP_UINT32("size", M48t59SysBusState, state.size, -1),
+ DEFINE_PROP_UINT32("type", M48t59SysBusState, state.type, -1),
+ DEFINE_PROP_HEX32( "io_base", M48t59SysBusState, state.io_base, 0),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void m48t59_register_devices(void)
+{
+ sysbus_register_withprop(&m48t59_info);
+ isa_qdev_register(&m48t59_isa_info);
+}
+
+device_init(m48t59_register_devices)
projects / qemu.git / blobdiff