* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "firmware_abi.h"
-#include "sysemu.h"
-#include "ppc_mac.h"
+#include "hw/hw.h"
+#include "hw/sparc/firmware_abi.h"
+#include "sysemu/sysemu.h"
+#include "hw/ppc/mac.h"
/* debug NVR */
//#define DEBUG_NVR
#ifdef DEBUG_NVR
-#define NVR_DPRINTF(fmt, args...) \
-do { printf("NVR: " fmt , ##args); } while (0)
+#define NVR_DPRINTF(fmt, ...) \
+ do { printf("NVR: " fmt , ## __VA_ARGS__); } while (0)
#else
-#define NVR_DPRINTF(fmt, args...)
+#define NVR_DPRINTF(fmt, ...)
#endif
-struct MacIONVRAMState {
- target_phys_addr_t size;
- int mem_index;
- uint8_t *data;
-};
+#define DEF_SYSTEM_SIZE 0xc10
/* Direct access to NVRAM */
-uint32_t macio_nvram_read (void *opaque, uint32_t addr)
+uint8_t macio_nvram_read(MacIONVRAMState *s, uint32_t addr)
{
- MacIONVRAMState *s = opaque;
uint32_t ret;
- if (addr < s->size)
+ if (addr < s->size) {
ret = s->data[addr];
- else
+ } else {
ret = -1;
- NVR_DPRINTF("read addr %04x val %x\n", addr, ret);
+ }
+ NVR_DPRINTF("read addr %04" PRIx32 " val %" PRIx8 "\n", addr, ret);
return ret;
}
-void macio_nvram_write (void *opaque, uint32_t addr, uint32_t val)
+void macio_nvram_write(MacIONVRAMState *s, uint32_t addr, uint8_t val)
{
- MacIONVRAMState *s = opaque;
-
- NVR_DPRINTF("write addr %04x val %x\n", addr, val);
- if (addr < s->size)
+ NVR_DPRINTF("write addr %04" PRIx32 " val %" PRIx8 "\n", addr, val);
+ if (addr < s->size) {
s->data[addr] = val;
+ }
}
/* macio style NVRAM device */
-static void macio_nvram_writeb (void *opaque,
- target_phys_addr_t addr, uint32_t value)
+static void macio_nvram_writeb(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
MacIONVRAMState *s = opaque;
- addr = (addr >> 4) & (s->size - 1);
+ addr = (addr >> s->it_shift) & (s->size - 1);
s->data[addr] = value;
- NVR_DPRINTF("writeb addr %04x val %x\n", (int)addr, value);
+ NVR_DPRINTF("writeb addr %04" PHYS_PRIx " val %" PRIx64 "\n", addr, value);
}
-static uint32_t macio_nvram_readb (void *opaque, target_phys_addr_t addr)
+static uint64_t macio_nvram_readb(void *opaque, hwaddr addr,
+ unsigned size)
{
MacIONVRAMState *s = opaque;
uint32_t value;
- addr = (addr >> 4) & (s->size - 1);
+ addr = (addr >> s->it_shift) & (s->size - 1);
value = s->data[addr];
NVR_DPRINTF("readb addr %04x val %x\n", (int)addr, value);
return value;
}
-static CPUWriteMemoryFunc *nvram_write[] = {
- &macio_nvram_writeb,
- &macio_nvram_writeb,
- &macio_nvram_writeb,
+static const MemoryRegionOps macio_nvram_ops = {
+ .read = macio_nvram_readb,
+ .write = macio_nvram_writeb,
+ .endianness = DEVICE_BIG_ENDIAN,
};
-static CPUReadMemoryFunc *nvram_read[] = {
- &macio_nvram_readb,
- &macio_nvram_readb,
- &macio_nvram_readb,
+static const VMStateDescription vmstate_macio_nvram = {
+ .name = "macio_nvram",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_VBUFFER_UINT32(data, MacIONVRAMState, 0, NULL, 0, size),
+ VMSTATE_END_OF_LIST()
+ }
};
-MacIONVRAMState *macio_nvram_init (int *mem_index, target_phys_addr_t size)
+
+static void macio_nvram_reset(DeviceState *dev)
{
- MacIONVRAMState *s;
-
- s = qemu_mallocz(sizeof(MacIONVRAMState));
- if (!s)
- return NULL;
- s->data = qemu_mallocz(size);
- if (!s->data) {
- qemu_free(s);
- return NULL;
- }
- s->size = size;
+}
+
+static void macio_nvram_realizefn(DeviceState *dev, Error **errp)
+{
+ SysBusDevice *d = SYS_BUS_DEVICE(dev);
+ MacIONVRAMState *s = MACIO_NVRAM(dev);
- s->mem_index = cpu_register_io_memory(0, nvram_read, nvram_write, s);
- *mem_index = s->mem_index;
+ s->data = g_malloc0(s->size);
- return s;
+ memory_region_init_io(&s->mem, &macio_nvram_ops, s, "macio-nvram",
+ s->size << s->it_shift);
+ sysbus_init_mmio(d, &s->mem);
}
-void macio_nvram_map (void *opaque, target_phys_addr_t mem_base)
+static void macio_nvram_unrealizefn(DeviceState *dev, Error **errp)
{
- MacIONVRAMState *s;
+ MacIONVRAMState *s = MACIO_NVRAM(dev);
- s = opaque;
- cpu_register_physical_memory(mem_base, s->size << 4, s->mem_index);
+ g_free(s->data);
+}
+
+static Property macio_nvram_properties[] = {
+ DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0),
+ DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0),
+ DEFINE_PROP_END_OF_LIST()
+};
+
+static void macio_nvram_class_init(ObjectClass *oc, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(oc);
+
+ dc->realize = macio_nvram_realizefn;
+ dc->unrealize = macio_nvram_unrealizefn;
+ dc->reset = macio_nvram_reset;
+ dc->vmsd = &vmstate_macio_nvram;
+ dc->props = macio_nvram_properties;
+}
+
+static const TypeInfo macio_nvram_type_info = {
+ .name = TYPE_MACIO_NVRAM,
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(MacIONVRAMState),
+ .class_init = macio_nvram_class_init,
+};
+
+static void macio_nvram_register_types(void)
+{
+ type_register_static(&macio_nvram_type_info);
}
/* Set up a system OpenBIOS NVRAM partition */
nvr->data[end++] = '\0';
end = start + ((end - start + 15) & ~15);
+ /* XXX: OpenBIOS is not able to grow up a partition. Leave some space for
+ new variables. */
+ if (end < DEF_SYSTEM_SIZE)
+ end = DEF_SYSTEM_SIZE;
OpenBIOS_finish_partition(part_header, end - start);
// free partition
end = len;
OpenBIOS_finish_partition(part_header, end - start);
}
+
+type_init(macio_nvram_register_types)
projects / qemu.git / blobdiff