hw: move NVRAM interfaces to hw/nvram/, configure with default-configs/

[qemu.git] / hw / mst_fpga.c

diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 7bcd5d75e819cf75d0e82c00d909cb85c15fcd84..1dd15054d0c52d55b557a4dfff8f369f2ff12a34 100644 (file)
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -6,9 +6,12 @@
  *                                    <akuster@mvista.com>
  *
  * This code is licensed under the GNU GPL v2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
  */
-#include "hw.h"
-#include "sysbus.h"
+#include "hw/hw.h"
+#include "hw/sysbus.h"
 
 /* Mainstone FPGA for extern irqs */
 #define FPGA_GPIO_PIN  0
@@ -34,6 +37,7 @@
 
 typedef struct mst_irq_state{
        SysBusDevice busdev;
+       MemoryRegion iomem;
 
        qemu_irq parent;
 
@@ -86,8 +90,8 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
 }
 
 
-static uint32_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t
+mst_fpga_readb(void *opaque, hwaddr addr, unsigned size)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
 
@@ -124,7 +128,8 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
 }
 
 static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+mst_fpga_writeb(void *opaque, hwaddr addr, uint64_t value,
+               unsigned size)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
        value &= 0xffffffff;
@@ -175,18 +180,12 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
        }
 }
 
-static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
-       mst_fpga_readb,
-       mst_fpga_readb,
-       mst_fpga_readb,
-};
-static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
-       mst_fpga_writeb,
-       mst_fpga_writeb,
-       mst_fpga_writeb,
+static const MemoryRegionOps mst_fpga_ops = {
+       .read = mst_fpga_readb,
+       .write = mst_fpga_writeb,
+       .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-
 static int mst_fpga_post_load(void *opaque, int version_id)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
@@ -198,7 +197,6 @@ static int mst_fpga_post_load(void *opaque, int version_id)
 static int mst_fpga_init(SysBusDevice *dev)
 {
        mst_irq_state *s;
-       int iomemtype;
 
        s = FROM_SYSBUS(mst_irq_state, dev);
 
@@ -210,9 +208,9 @@ static int mst_fpga_init(SysBusDevice *dev)
        /* alloc the external 16 irqs */
        qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
 
-       iomemtype = cpu_register_io_memory(mst_fpga_readfn,
-               mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
-       sysbus_init_mmio(dev, 0x00100000, iomemtype);
+       memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
+                           "fpga", 0x00100000);
+       sysbus_init_mmio(dev, &s->iomem);
        return 0;
 }
 
@@ -240,16 +238,26 @@ static VMStateDescription vmstate_mst_fpga_regs = {
        },
 };
 
-static SysBusDeviceInfo mst_fpga_info = {
-       .init = mst_fpga_init,
-       .qdev.name = "mainstone-fpga",
-       .qdev.desc = "Mainstone II FPGA",
-       .qdev.size = sizeof(mst_irq_state),
-       .qdev.vmsd = &vmstate_mst_fpga_regs,
+static void mst_fpga_class_init(ObjectClass *klass, void *data)
+{
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+    k->init = mst_fpga_init;
+    dc->desc = "Mainstone II FPGA";
+    dc->vmsd = &vmstate_mst_fpga_regs;
+}
+
+static const TypeInfo mst_fpga_info = {
+    .name          = "mainstone-fpga",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(mst_irq_state),
+    .class_init    = mst_fpga_class_init,
 };
 
-static void mst_fpga_register(void)
+static void mst_fpga_register_types(void)
 {
-       sysbus_register_withprop(&mst_fpga_info);
+    type_register_static(&mst_fpga_info);
 }
-device_init(mst_fpga_register);
+
+type_init(mst_fpga_register_types)