#define MST_PCMCIA0 0xe0
#define MST_PCMCIA1 0xe4
+#define MST_PCMCIAx_READY (1 << 10)
+#define MST_PCMCIAx_nCD (1 << 5)
+
+#define MST_PCMCIA_CD0_IRQ 9
+#define MST_PCMCIA_CD1_IRQ 13
+
typedef struct mst_irq_state{
SysBusDevice busdev;
mst_fpga_set_irq(void *opaque, int irq, int level)
{
mst_irq_state *s = (mst_irq_state *)opaque;
- uint32_t oldint = s->intsetclr;
+ uint32_t oldint = s->intsetclr & s->intmskena;
if (level)
s->prev_level |= 1u << irq;
else
s->prev_level &= ~(1u << irq);
+ switch(irq) {
+ case MST_PCMCIA_CD0_IRQ:
+ if (level)
+ s->pcmcia0 &= ~MST_PCMCIAx_nCD;
+ else
+ s->pcmcia0 |= MST_PCMCIAx_nCD;
+ break;
+ case MST_PCMCIA_CD1_IRQ:
+ if (level)
+ s->pcmcia1 &= ~MST_PCMCIAx_nCD;
+ else
+ s->pcmcia1 |= MST_PCMCIAx_nCD;
+ break;
+ }
+
if ((s->intmskena & (1u << irq)) && level)
s->intsetclr |= 1u << irq;
case MST_MSCRD:
s->mscrd = value;
break;
- case MST_INTMSKENA: /* Mask interupt */
+ case MST_INTMSKENA: /* Mask interrupt */
s->intmskena = (value & 0xFEEFF);
qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
break;
case MST_INTSETCLR: /* clear or set interrupt */
s->intsetclr = (value & 0xFEEFF);
- qemu_set_irq(s->parent, s->intsetclr);
+ qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
break;
+ /* For PCMCIAx allow the to change only power and reset */
case MST_PCMCIA0:
- s->pcmcia0 = value;
+ s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
break;
case MST_PCMCIA1:
- s->pcmcia1 = value;
+ s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
break;
default:
printf("Mainstone - mst_fpga_writeb: Bad register offset "
s = FROM_SYSBUS(mst_irq_state, dev);
+ s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+ s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+
sysbus_init_irq(dev, &s->parent);
/* alloc the external 16 irqs */