prepare for future GPLv2+ relicensing

[qemu.git] / hw / mst_fpga.c

diff --git a/hw/mst_fpga.c b/hw/mst_fpga.c
index 407bac97168bc81e850f6d6797897b9d7e9d9147..8bfa5dda3718bb114f115a9249ee89d6443abaee 100644 (file)
--- a/hw/mst_fpga.c
+++ b/hw/mst_fpga.c
@@ -6,6 +6,9 @@
  *                                    <akuster@mvista.com>
  *
  * This code is licensed under the GNU GPL v2.
+ *
+ * Contributions after 2012-01-13 are licensed under the terms of the
+ * GNU GPL, version 2 or (at your option) any later version.
  */
 #include "hw.h"
 #include "sysbus.h"
@@ -26,8 +29,15 @@
 #define MST_PCMCIA0            0xe0
 #define MST_PCMCIA1            0xe4
 
+#define MST_PCMCIAx_READY      (1 << 10)
+#define MST_PCMCIAx_nCD                (1 << 5)
+
+#define MST_PCMCIA_CD0_IRQ     9
+#define MST_PCMCIA_CD1_IRQ     13
+
 typedef struct mst_irq_state{
        SysBusDevice busdev;
+       MemoryRegion iomem;
 
        qemu_irq parent;
 
@@ -57,6 +67,21 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
        else
                s->prev_level &= ~(1u << irq);
 
+       switch(irq) {
+       case MST_PCMCIA_CD0_IRQ:
+               if (level)
+                       s->pcmcia0 &= ~MST_PCMCIAx_nCD;
+               else
+                       s->pcmcia0 |=  MST_PCMCIAx_nCD;
+               break;
+       case MST_PCMCIA_CD1_IRQ:
+               if (level)
+                       s->pcmcia1 &= ~MST_PCMCIAx_nCD;
+               else
+                       s->pcmcia1 |=  MST_PCMCIAx_nCD;
+               break;
+       }
+
        if ((s->intmskena & (1u << irq)) && level)
                s->intsetclr |= 1u << irq;
 
@@ -65,8 +90,8 @@ mst_fpga_set_irq(void *opaque, int irq, int level)
 }
 
 
-static uint32_t
-mst_fpga_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t
+mst_fpga_readb(void *opaque, target_phys_addr_t addr, unsigned size)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
 
@@ -97,13 +122,14 @@ mst_fpga_readb(void *opaque, target_phys_addr_t addr)
                return s->pcmcia1;
        default:
                printf("Mainstone - mst_fpga_readb: Bad register offset "
-                       "0x" TARGET_FMT_plx " \n", addr);
+                       "0x" TARGET_FMT_plx "\n", addr);
        }
        return 0;
 }
 
 static void
-mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
+mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint64_t value,
+               unsigned size)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
        value &= 0xffffffff;
@@ -133,7 +159,7 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
        case MST_MSCRD:
                s->mscrd =  value;
                break;
-       case MST_INTMSKENA:     /* Mask interupt */
+       case MST_INTMSKENA:     /* Mask interrupt */
                s->intmskena = (value & 0xFEEFF);
                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
                break;
@@ -141,30 +167,25 @@ mst_fpga_writeb(void *opaque, target_phys_addr_t addr, uint32_t value)
                s->intsetclr = (value & 0xFEEFF);
                qemu_set_irq(s->parent, s->intsetclr & s->intmskena);
                break;
+               /* For PCMCIAx allow the to change only power and reset */
        case MST_PCMCIA0:
-               s->pcmcia0 = value;
+               s->pcmcia0 = (value & 0x1f) | (s->pcmcia0 & ~0x1f);
                break;
        case MST_PCMCIA1:
-               s->pcmcia1 = value;
+               s->pcmcia1 = (value & 0x1f) | (s->pcmcia1 & ~0x1f);
                break;
        default:
                printf("Mainstone - mst_fpga_writeb: Bad register offset "
-                       "0x" TARGET_FMT_plx " \n", addr);
+                       "0x" TARGET_FMT_plx "\n", addr);
        }
 }
 
-static CPUReadMemoryFunc * const mst_fpga_readfn[] = {
-       mst_fpga_readb,
-       mst_fpga_readb,
-       mst_fpga_readb,
-};
-static CPUWriteMemoryFunc * const mst_fpga_writefn[] = {
-       mst_fpga_writeb,
-       mst_fpga_writeb,
-       mst_fpga_writeb,
+static const MemoryRegionOps mst_fpga_ops = {
+       .read = mst_fpga_readb,
+       .write = mst_fpga_writeb,
+       .endianness = DEVICE_NATIVE_ENDIAN,
 };
 
-
 static int mst_fpga_post_load(void *opaque, int version_id)
 {
        mst_irq_state *s = (mst_irq_state *) opaque;
@@ -176,18 +197,20 @@ static int mst_fpga_post_load(void *opaque, int version_id)
 static int mst_fpga_init(SysBusDevice *dev)
 {
        mst_irq_state *s;
-       int iomemtype;
 
        s = FROM_SYSBUS(mst_irq_state, dev);
 
+       s->pcmcia0 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+       s->pcmcia1 = MST_PCMCIAx_READY | MST_PCMCIAx_nCD;
+
        sysbus_init_irq(dev, &s->parent);
 
        /* alloc the external 16 irqs */
        qdev_init_gpio_in(&dev->qdev, mst_fpga_set_irq, MST_NUM_IRQS);
 
-       iomemtype = cpu_register_io_memory(mst_fpga_readfn,
-               mst_fpga_writefn, s, DEVICE_NATIVE_ENDIAN);
-       sysbus_init_mmio(dev, 0x00100000, iomemtype);
+       memory_region_init_io(&s->iomem, &mst_fpga_ops, s,
+                           "fpga", 0x00100000);
+       sysbus_init_mmio(dev, &s->iomem);
        return 0;
 }