#include "arm-misc.h"
#include "omap.h"
#include "sysemu.h"
-#include "qemu-timer.h"
-#include "qemu-char.h"
#include "soc_dma.h"
-/* We use pc-style serial ports. */
-#include "pc.h"
#include "blockdev.h"
-#include "range.h"
+#include "qemu/range.h"
#include "sysbus.h"
/* Should signal the TCMI/GPMC */
-uint32_t omap_badwidth_read8(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read8(void *opaque, hwaddr addr)
{
uint8_t ret;
return ret;
}
-void omap_badwidth_write8(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write8(void *opaque, hwaddr addr,
uint32_t value)
{
uint8_t val8 = value;
cpu_physical_memory_write(addr, (void *) &val8, 1);
}
-uint32_t omap_badwidth_read16(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read16(void *opaque, hwaddr addr)
{
uint16_t ret;
return ret;
}
-void omap_badwidth_write16(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write16(void *opaque, hwaddr addr,
uint32_t value)
{
uint16_t val16 = value;
cpu_physical_memory_write(addr, (void *) &val16, 2);
}
-uint32_t omap_badwidth_read32(void *opaque, target_phys_addr_t addr)
+uint32_t omap_badwidth_read32(void *opaque, hwaddr addr)
{
uint32_t ret;
return ret;
}
-void omap_badwidth_write32(void *opaque, target_phys_addr_t addr,
+void omap_badwidth_write32(void *opaque, hwaddr addr,
uint32_t value)
{
OMAP_32B_REG(addr);
timer->rate = omap_clk_getrate(timer->clk);
}
-static uint64_t omap_mpu_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpu_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
return 0;
}
-static void omap_mpu_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpu_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *) opaque;
}
static struct omap_mpu_timer_s *omap_mpu_timer_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_mpu_timer_s *s = (struct omap_mpu_timer_s *)
int reset;
};
-static uint64_t omap_wd_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_wd_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
return 0;
}
-static void omap_wd_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_wd_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *) opaque;
}
static struct omap_watchdog_timer_s *omap_wd_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_watchdog_timer_s *s = (struct omap_watchdog_timer_s *)
MemoryRegion iomem;
};
-static uint64_t omap_os_timer_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_os_timer_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
return 0;
}
-static void omap_os_timer_write(void *opaque, target_phys_addr_t addr,
+static void omap_os_timer_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *) opaque;
}
static struct omap_32khz_timer_s *omap_os_timer_init(MemoryRegion *memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq irq, omap_clk clk)
{
struct omap_32khz_timer_s *s = (struct omap_32khz_timer_s *)
}
/* Ultra Low-Power Device Module */
-static uint64_t omap_ulpd_pm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_ulpd_pm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
omap_clk_canidle(omap_findclk(s, "usb_clk0"), (~value >> 3) & 1);
}
-static void omap_ulpd_pm_write(void *opaque, target_phys_addr_t addr,
+static void omap_ulpd_pm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
}
static void omap_ulpd_pm_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->ulpd_pm_iomem, &omap_ulpd_pm_ops, mpu,
}
/* OMAP Pin Configuration */
-static uint64_t omap_pin_cfg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pin_cfg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
omap_clk_onoff(omap_findclk(s, "usb_hhc_ck"), (value >> 9) & 1);
}
-static void omap_pin_cfg_write(void *opaque, target_phys_addr_t addr,
+static void omap_pin_cfg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
}
static void omap_pin_cfg_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->pin_cfg_iomem, &omap_pin_cfg_ops, mpu,
}
/* Device Identification, Die Identification */
-static uint64_t omap_id_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_id_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_id_write(void *opaque, target_phys_addr_t addr,
+static void omap_id_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
if (size != 4) {
}
/* MPUI Control (Dummy) */
-static uint64_t omap_mpui_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_mpui_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
s->mpui_ctrl = 0x0003ff1b;
}
-static void omap_mpui_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_mpui_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->mpui_iomem, &omap_mpui_ops, mpu,
uint16_t enh_control;
};
-static uint64_t omap_tipb_bridge_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tipb_bridge_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
return 0;
}
-static void omap_tipb_bridge_write(void *opaque, target_phys_addr_t addr,
+static void omap_tipb_bridge_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *) opaque;
}
static struct omap_tipb_bridge_s *omap_tipb_bridge_init(
- MemoryRegion *memory, target_phys_addr_t base,
+ MemoryRegion *memory, hwaddr base,
qemu_irq abort_irq, omap_clk clk)
{
struct omap_tipb_bridge_s *s = (struct omap_tipb_bridge_s *)
}
/* Dummy Traffic Controller's Memory Interface */
-static uint64_t omap_tcmi_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_tcmi_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
return 0;
}
-static void omap_tcmi_write(void *opaque, target_phys_addr_t addr,
+static void omap_tcmi_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
mpu->tcmi_regs[0x40 >> 2] = 0x00000000;
}
-static void omap_tcmi_init(MemoryRegion *memory, target_phys_addr_t base,
+static void omap_tcmi_init(MemoryRegion *memory, hwaddr base,
struct omap_mpu_state_s *mpu)
{
memory_region_init_io(&mpu->tcmi_iomem, &omap_tcmi_ops, mpu,
}
/* Digital phase-locked loops control */
-static uint64_t omap_dpll_read(void *opaque, target_phys_addr_t addr,
+struct dpll_ctl_s {
+ MemoryRegion iomem;
+ uint16_t mode;
+ omap_clk dpll;
+};
+
+static uint64_t omap_dpll_read(void *opaque, hwaddr addr,
unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
return 0;
}
-static void omap_dpll_write(void *opaque, target_phys_addr_t addr,
+static void omap_dpll_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct dpll_ctl_s *s = (struct dpll_ctl_s *) opaque;
omap_clk_setrate(s->dpll, 1, 1);
}
-static void omap_dpll_init(MemoryRegion *memory, struct dpll_ctl_s *s,
- target_phys_addr_t base, omap_clk clk)
+static struct dpll_ctl_s *omap_dpll_init(MemoryRegion *memory,
+ hwaddr base, omap_clk clk)
{
+ struct dpll_ctl_s *s = g_malloc0(sizeof(*s));
memory_region_init_io(&s->iomem, &omap_dpll_ops, s, "omap-dpll", 0x100);
s->dpll = clk;
omap_dpll_reset(s);
memory_region_add_subregion(memory, base, &s->iomem);
+ return s;
}
/* MPU Clock/Reset/Power Mode Control */
-static uint64_t omap_clkm_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkm_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
{
omap_clk clk;
- if (value & (1 << 11)) /* SETARM_IDLE */
- cpu_interrupt(s->env, CPU_INTERRUPT_HALT);
+ if (value & (1 << 11)) { /* SETARM_IDLE */
+ cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT);
+ }
if (!(value & (1 << 10))) /* WKUP_MODE */
qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */
}
}
-static void omap_clkm_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkm_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_clkdsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
case 0x18: /* DSP_SYSST */
return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start |
- (s->env->halted << 6); /* Quite useless... */
+ (s->cpu->env.halted << 6); /* Quite useless... */
}
OMAP_BAD_REG(addr);
SET_ONOFF("dspxor_ck", 1); /* EN_XORPCK */
}
-static void omap_clkdsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_clkdsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
s->clkm.dsp_rstct2 = 0x0000;
}
-static void omap_clkm_init(MemoryRegion *memory, target_phys_addr_t mpu_base,
- target_phys_addr_t dsp_base, struct omap_mpu_state_s *s)
+static void omap_clkm_init(MemoryRegion *memory, hwaddr mpu_base,
+ hwaddr dsp_base, struct omap_mpu_state_s *s)
{
memory_region_init_io(&s->clkm_iomem, &omap_clkm_ops, s,
"omap-clkm", 0x100);
s->row_latch = ~rows;
}
-static uint64_t omap_mpuio_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpuio_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
return 0;
}
-static void omap_mpuio_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpuio_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_mpuio_s *s = (struct omap_mpuio_s *) opaque;
omap_mpuio_kbd_update(s);
}
-struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
- target_phys_addr_t base,
+static struct omap_mpuio_s *omap_mpuio_init(MemoryRegion *memory,
+ hwaddr base,
qemu_irq kbd_int, qemu_irq gpio_int, qemu_irq wakeup,
omap_clk clk)
{
}
}
-static uint64_t omap_uwire_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_uwire_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
return 0;
}
-static void omap_uwire_write(void *opaque, target_phys_addr_t addr,
+static void omap_uwire_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_uwire_s *s = (struct omap_uwire_s *) opaque;
}
static struct omap_uwire_s *omap_uwire_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq dma,
omap_clk clk)
}
/* Pseudonoise Pulse-Width Light Modulator */
-static void omap_pwl_update(struct omap_mpu_state_s *s)
+struct omap_pwl_s {
+ MemoryRegion iomem;
+ uint8_t output;
+ uint8_t level;
+ uint8_t enable;
+ int clk;
+};
+
+static void omap_pwl_update(struct omap_pwl_s *s)
{
- int output = (s->pwl.clk && s->pwl.enable) ? s->pwl.level : 0;
+ int output = (s->clk && s->enable) ? s->level : 0;
- if (output != s->pwl.output) {
- s->pwl.output = output;
+ if (output != s->output) {
+ s->output = output;
printf("%s: Backlight now at %i/256\n", __FUNCTION__, output);
}
}
-static uint64_t omap_pwl_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_pwl_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
switch (offset) {
case 0x00: /* PWL_LEVEL */
- return s->pwl.level;
+ return s->level;
case 0x04: /* PWL_CTRL */
- return s->pwl.enable;
+ return s->enable;
}
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_pwl_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwl_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
switch (offset) {
case 0x00: /* PWL_LEVEL */
- s->pwl.level = value;
+ s->level = value;
omap_pwl_update(s);
break;
case 0x04: /* PWL_CTRL */
- s->pwl.enable = value & 1;
+ s->enable = value & 1;
omap_pwl_update(s);
break;
default:
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void omap_pwl_reset(struct omap_mpu_state_s *s)
+static void omap_pwl_reset(struct omap_pwl_s *s)
{
- s->pwl.output = 0;
- s->pwl.level = 0;
- s->pwl.enable = 0;
- s->pwl.clk = 1;
+ s->output = 0;
+ s->level = 0;
+ s->enable = 0;
+ s->clk = 1;
omap_pwl_update(s);
}
static void omap_pwl_clk_update(void *opaque, int line, int on)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_pwl_s *s = (struct omap_pwl_s *) opaque;
- s->pwl.clk = on;
+ s->clk = on;
omap_pwl_update(s);
}
-static void omap_pwl_init(MemoryRegion *system_memory,
- target_phys_addr_t base, struct omap_mpu_state_s *s,
- omap_clk clk)
+static struct omap_pwl_s *omap_pwl_init(MemoryRegion *system_memory,
+ hwaddr base,
+ omap_clk clk)
{
+ struct omap_pwl_s *s = g_malloc0(sizeof(*s));
+
omap_pwl_reset(s);
- memory_region_init_io(&s->pwl_iomem, &omap_pwl_ops, s,
+ memory_region_init_io(&s->iomem, &omap_pwl_ops, s,
"omap-pwl", 0x800);
- memory_region_add_subregion(system_memory, base, &s->pwl_iomem);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
omap_clk_adduser(clk, qemu_allocate_irqs(omap_pwl_clk_update, s, 1)[0]);
+ return s;
}
/* Pulse-Width Tone module */
-static uint64_t omap_pwt_read(void *opaque, target_phys_addr_t addr,
+struct omap_pwt_s {
+ MemoryRegion iomem;
+ uint8_t frc;
+ uint8_t vrc;
+ uint8_t gcr;
+ omap_clk clk;
+};
+
+static uint64_t omap_pwt_read(void *opaque, hwaddr addr,
unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
switch (offset) {
case 0x00: /* FRC */
- return s->pwt.frc;
+ return s->frc;
case 0x04: /* VCR */
- return s->pwt.vrc;
+ return s->vrc;
case 0x08: /* GCR */
- return s->pwt.gcr;
+ return s->gcr;
}
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_pwt_write(void *opaque, target_phys_addr_t addr,
+static void omap_pwt_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
- struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
+ struct omap_pwt_s *s = (struct omap_pwt_s *) opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
if (size != 1) {
switch (offset) {
case 0x00: /* FRC */
- s->pwt.frc = value & 0x3f;
+ s->frc = value & 0x3f;
break;
case 0x04: /* VRC */
- if ((value ^ s->pwt.vrc) & 1) {
+ if ((value ^ s->vrc) & 1) {
if (value & 1)
printf("%s: %iHz buzz on\n", __FUNCTION__, (int)
/* 1.5 MHz from a 12-MHz or 13-MHz PWT_CLK */
- ((omap_clk_getrate(s->pwt.clk) >> 3) /
+ ((omap_clk_getrate(s->clk) >> 3) /
/* Pre-multiplexer divider */
- ((s->pwt.gcr & 2) ? 1 : 154) /
+ ((s->gcr & 2) ? 1 : 154) /
/* Octave multiplexer */
(2 << (value & 3)) *
/* 101/107 divider */
else
printf("%s: silence!\n", __FUNCTION__);
}
- s->pwt.vrc = value & 0x7f;
+ s->vrc = value & 0x7f;
break;
case 0x08: /* GCR */
- s->pwt.gcr = value & 3;
+ s->gcr = value & 3;
break;
default:
OMAP_BAD_REG(addr);
.endianness = DEVICE_NATIVE_ENDIAN,
};
-static void omap_pwt_reset(struct omap_mpu_state_s *s)
+static void omap_pwt_reset(struct omap_pwt_s *s)
{
- s->pwt.frc = 0;
- s->pwt.vrc = 0;
- s->pwt.gcr = 0;
+ s->frc = 0;
+ s->vrc = 0;
+ s->gcr = 0;
}
-static void omap_pwt_init(MemoryRegion *system_memory,
- target_phys_addr_t base, struct omap_mpu_state_s *s,
- omap_clk clk)
+static struct omap_pwt_s *omap_pwt_init(MemoryRegion *system_memory,
+ hwaddr base,
+ omap_clk clk)
{
- s->pwt.clk = clk;
+ struct omap_pwt_s *s = g_malloc0(sizeof(*s));
+ s->clk = clk;
omap_pwt_reset(s);
- memory_region_init_io(&s->pwt_iomem, &omap_pwt_ops, s,
+ memory_region_init_io(&s->iomem, &omap_pwt_ops, s,
"omap-pwt", 0x800);
- memory_region_add_subregion(system_memory, base, &s->pwt_iomem);
+ memory_region_add_subregion(system_memory, base, &s->iomem);
+ return s;
}
/* Real-time Clock module */
printf("%s: conversion failed\n", __FUNCTION__);
}
-static uint64_t omap_rtc_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_rtc_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
return 0;
}
-static void omap_rtc_write(void *opaque, target_phys_addr_t addr,
+static void omap_rtc_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_rtc_s *s = (struct omap_rtc_s *) opaque;
s->pm_am = 0;
s->auto_comp = 0;
s->round = 0;
- s->tick = qemu_get_clock_ms(rt_clock);
+ s->tick = qemu_get_clock_ms(rtc_clock);
memset(&s->alarm_tm, 0, sizeof(s->alarm_tm));
s->alarm_tm.tm_mday = 0x01;
s->status = 1 << 7;
}
static struct omap_rtc_s *omap_rtc_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq timerirq, qemu_irq alarmirq,
omap_clk clk)
{
s->irq = timerirq;
s->alarm = alarmirq;
- s->clk = qemu_new_timer_ms(rt_clock, omap_rtc_tick, s);
+ s->clk = qemu_new_timer_ms(rtc_clock, omap_rtc_tick, s);
omap_rtc_reset(s);
omap_mcbsp_rx_stop(s);
}
-static uint64_t omap_mcbsp_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mcbsp_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
return 0;
}
-static void omap_mcbsp_writeh(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writeh(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
OMAP_BAD_REG(addr);
}
-static void omap_mcbsp_writew(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_writew(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_mcbsp_s *s = (struct omap_mcbsp_s *) opaque;
omap_badwidth_write16(opaque, addr, value);
}
-static void omap_mcbsp_write(void *opaque, target_phys_addr_t addr,
+static void omap_mcbsp_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
switch (size) {
}
static struct omap_mcbsp_s *omap_mcbsp_init(MemoryRegion *system_memory,
- target_phys_addr_t base,
+ hwaddr base,
qemu_irq txirq, qemu_irq rxirq,
qemu_irq *dma, omap_clk clk)
{
struct omap_lpg_s *s = opaque;
if (s->cycle)
- qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->period - s->on);
+ qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->period - s->on);
else
- qemu_mod_timer(s->tm, qemu_get_clock_ms(rt_clock) + s->on);
+ qemu_mod_timer(s->tm, qemu_get_clock_ms(vm_clock) + s->on);
s->cycle = !s->cycle;
printf("%s: LED is %s\n", __FUNCTION__, s->cycle ? "on" : "off");
omap_lpg_update(s);
}
-static uint64_t omap_lpg_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_lpg_read(void *opaque, hwaddr addr,
unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
return 0;
}
-static void omap_lpg_write(void *opaque, target_phys_addr_t addr,
+static void omap_lpg_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
struct omap_lpg_s *s = (struct omap_lpg_s *) opaque;
}
static struct omap_lpg_s *omap_lpg_init(MemoryRegion *system_memory,
- target_phys_addr_t base, omap_clk clk)
+ hwaddr base, omap_clk clk)
{
struct omap_lpg_s *s = (struct omap_lpg_s *)
g_malloc0(sizeof(struct omap_lpg_s));
- s->tm = qemu_new_timer_ms(rt_clock, omap_lpg_tick, s);
+ s->tm = qemu_new_timer_ms(vm_clock, omap_lpg_tick, s);
omap_lpg_reset(s);
}
/* MPUI Peripheral Bridge configuration */
-static uint64_t omap_mpui_io_read(void *opaque, target_phys_addr_t addr,
+static uint64_t omap_mpui_io_read(void *opaque, hwaddr addr,
unsigned size)
{
if (size != 2) {
return 0;
}
-static void omap_mpui_io_write(void *opaque, target_phys_addr_t addr,
+static void omap_mpui_io_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
/* FIXME: infinite loop */
omap_mpui_reset(mpu);
omap_tipb_bridge_reset(mpu->private_tipb);
omap_tipb_bridge_reset(mpu->public_tipb);
- omap_dpll_reset(&mpu->dpll[0]);
- omap_dpll_reset(&mpu->dpll[1]);
- omap_dpll_reset(&mpu->dpll[2]);
+ omap_dpll_reset(mpu->dpll[0]);
+ omap_dpll_reset(mpu->dpll[1]);
+ omap_dpll_reset(mpu->dpll[2]);
omap_uart_reset(mpu->uart[0]);
omap_uart_reset(mpu->uart[1]);
omap_uart_reset(mpu->uart[2]);
omap_mmc_reset(mpu->mmc);
omap_mpuio_reset(mpu->mpuio);
omap_uwire_reset(mpu->microwire);
- omap_pwl_reset(mpu);
- omap_pwt_reset(mpu);
- omap_i2c_reset(mpu->i2c[0]);
+ omap_pwl_reset(mpu->pwl);
+ omap_pwt_reset(mpu->pwt);
omap_rtc_reset(mpu->rtc);
omap_mcbsp_reset(mpu->mcbsp1);
omap_mcbsp_reset(mpu->mcbsp2);
omap_lpg_reset(mpu->led[0]);
omap_lpg_reset(mpu->led[1]);
omap_clkm_reset(mpu);
- cpu_reset(mpu->env);
+ cpu_reset(CPU(mpu->cpu));
}
static const struct omap_map_s {
- target_phys_addr_t phys_dsp;
- target_phys_addr_t phys_mpu;
+ hwaddr phys_dsp;
+ hwaddr phys_mpu;
uint32_t size;
const char *name;
} omap15xx_dsp_mm[] = {
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- if (mpu->env->halted)
- cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB);
+ if (mpu->cpu->env.halted) {
+ cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB);
+ }
}
static const struct dma_irq_map omap1_dma_irq_map[] = {
/* DMA ports for OMAP1 */
static int omap_validate_emiff_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFF_BASE, s->sdram_size, addr);
}
static int omap_validate_emifs_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_EMIFS_BASE, OMAP_EMIFF_BASE - OMAP_EMIFS_BASE,
addr);
}
static int omap_validate_imif_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_IMIF_BASE, s->sram_size, addr);
}
static int omap_validate_tipb_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xfffb0000, 0xffff0000 - 0xfffb0000, addr);
}
static int omap_validate_local_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(OMAP_LOCALBUS_BASE, 0x1000000, addr);
}
static int omap_validate_tipb_mpui_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return range_covers_byte(0xe1010000, 0xe1020004 - 0xe1010000, addr);
}
/* Core */
s->mpu_model = omap310;
- s->env = cpu_init(core);
- if (!s->env) {
+ s->cpu = cpu_arm_init(core);
+ if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
omap_clk_init(s);
/* Memory-mapped stuff */
- memory_region_init_ram(&s->emiff_ram, NULL, "omap1.dram", s->sdram_size);
+ memory_region_init_ram(&s->emiff_ram, "omap1.dram", s->sdram_size);
+ vmstate_register_ram_global(&s->emiff_ram);
memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram);
- memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size);
+ memory_region_init_ram(&s->imif_ram, "omap1.sram", s->sram_size);
+ vmstate_register_ram_global(&s->imif_ram);
memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram);
omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s);
- cpu_irq = arm_pic_init_cpu(s->env);
+ cpu_irq = arm_pic_init_cpu(s->cpu);
s->ih[0] = qdev_create(NULL, "omap-intc");
qdev_prop_set_uint32(s->ih[0], "size", 0x100);
qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck"));
"uart3",
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
- omap_dpll_init(system_memory,
- &s->dpll[0], 0xfffecf00, omap_findclk(s, "dpll1"));
- omap_dpll_init(system_memory,
- &s->dpll[1], 0xfffed000, omap_findclk(s, "dpll2"));
- omap_dpll_init(system_memory,
- &s->dpll[2], 0xfffed100, omap_findclk(s, "dpll3"));
+ s->dpll[0] = omap_dpll_init(system_memory, 0xfffecf00,
+ omap_findclk(s, "dpll1"));
+ s->dpll[1] = omap_dpll_init(system_memory, 0xfffed000,
+ omap_findclk(s, "dpll2"));
+ s->dpll[2] = omap_dpll_init(system_memory, 0xfffed100,
+ omap_findclk(s, "dpll3"));
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
qdev_get_gpio_in(s->ih[1], OMAP_INT_uWireRX),
s->drq[OMAP_DMA_UWIRE_TX], omap_findclk(s, "mpuper_ck"));
- omap_pwl_init(system_memory, 0xfffb5800, s, omap_findclk(s, "armxor_ck"));
- omap_pwt_init(system_memory, 0xfffb6000, s, omap_findclk(s, "armxor_ck"));
-
- s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,
- qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
- &s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
+ s->pwl = omap_pwl_init(system_memory, 0xfffb5800,
+ omap_findclk(s, "armxor_ck"));
+ s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
+ omap_findclk(s, "armxor_ck"));
+
+ s->i2c[0] = qdev_create(NULL, "omap_i2c");
+ qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
+ qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck"));
+ qdev_init_nofail(s->i2c[0]);
+ busdev = sysbus_from_qdev(s->i2c[0]);
+ sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
+ sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
+ sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
+ sysbus_mmio_map(busdev, 0, 0xfffb3800);
s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),
projects / qemu.git / blobdiff