* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
-#include "blockdev.h"
+#include "sysemu/blockdev.h"
#include "hw.h"
#include "arm-misc.h"
#include "omap.h"
-#include "sysemu.h"
-#include "qemu-timer.h"
+#include "sysemu/sysemu.h"
+#include "qemu/timer.h"
#include "qemu-char.h"
#include "flash.h"
#include "soc_dma.h"
/* Enhanced Audio Controller (CODEC only) */
struct omap_eac_s {
qemu_irq irq;
+ MemoryRegion iomem;
uint16_t sysconfig;
uint8_t config[4];
omap_eac_interrupt_update(s);
}
-static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_eac_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
uint32_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x000: /* CPCFR1 */
return s->config[0];
return 0;
}
-static void omap_eac_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_eac_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_eac_s *s = (struct omap_eac_s *) opaque;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x098: /* APD1LCR */
case 0x09c: /* APD1RCR */
}
}
-static CPUReadMemoryFunc * const omap_eac_readfn[] = {
- omap_badwidth_read16,
- omap_eac_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_eac_writefn[] = {
- omap_badwidth_write16,
- omap_eac_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_eac_ops = {
+ .read = omap_eac_read,
+ .write = omap_eac_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
{
- int iomemtype;
struct omap_eac_s *s = (struct omap_eac_s *)
- qemu_mallocz(sizeof(struct omap_eac_s));
+ g_malloc0(sizeof(struct omap_eac_s));
s->irq = irq;
s->codec.rxdrq = *drq ++;
AUD_register_card("OMAP EAC", &s->codec.card);
- iomemtype = cpu_register_io_memory(omap_eac_readfn,
- omap_eac_writefn, s, DEVICE_NATIVE_ENDIAN);
- omap_l4_attach(ta, 0, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_eac_ops, s, "omap.eac",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach(ta, 0, &s->iomem);
return s;
}
/* STI/XTI (emulation interface) console - reverse engineered only */
struct omap_sti_s {
qemu_irq irq;
+ MemoryRegion iomem;
+ MemoryRegion iomem_fifo;
CharDriverState *chr;
uint32_t sysconfig;
omap_sti_interrupt_update(s);
}
-static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_sti_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* STI_REVISION */
return 0x10;
return 0;
}
-static void omap_sti_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_sti_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x00: /* STI_REVISION */
case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
}
}
-static CPUReadMemoryFunc * const omap_sti_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_sti_read,
-};
-
-static CPUWriteMemoryFunc * const omap_sti_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_sti_write,
+static const MemoryRegionOps omap_sti_ops = {
+ .read = omap_sti_read,
+ .write = omap_sti_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_sti_fifo_read(void *opaque, hwaddr addr,
+ unsigned size)
{
OMAP_BAD_REG(addr);
return 0;
}
-static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_sti_fifo_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_sti_s *s = (struct omap_sti_s *) opaque;
int ch = addr >> 6;
uint8_t byte = value;
+ if (size != 1) {
+ return omap_badwidth_write8(opaque, addr, size);
+ }
+
if (ch == STI_TRACE_CONTROL_CHANNEL) {
/* Flush channel <i>value</i>. */
- qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
+ qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
if (value == 0xc0 || value == 0xc3) {
/* Open channel <i>ch</i>. */
} else if (value == 0x00)
- qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
+ qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
else
- qemu_chr_write(s->chr, &byte, 1);
+ qemu_chr_fe_write(s->chr, &byte, 1);
}
}
-static CPUReadMemoryFunc * const omap_sti_fifo_readfn[] = {
- omap_sti_fifo_read,
- omap_badwidth_read8,
- omap_badwidth_read8,
-};
-
-static CPUWriteMemoryFunc * const omap_sti_fifo_writefn[] = {
- omap_sti_fifo_write,
- omap_badwidth_write8,
- omap_badwidth_write8,
+static const MemoryRegionOps omap_sti_fifo_ops = {
+ .read = omap_sti_fifo_read,
+ .write = omap_sti_fifo_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
- target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
+ MemoryRegion *sysmem,
+ hwaddr channel_base, qemu_irq irq, omap_clk clk,
CharDriverState *chr)
{
- int iomemtype;
struct omap_sti_s *s = (struct omap_sti_s *)
- qemu_mallocz(sizeof(struct omap_sti_s));
+ g_malloc0(sizeof(struct omap_sti_s));
s->irq = irq;
omap_sti_reset(s);
- s->chr = chr ?: qemu_chr_open("null", "null", NULL);
+ s->chr = chr ?: qemu_chr_new("null", "null", NULL);
- iomemtype = l4_register_io_memory(omap_sti_readfn,
- omap_sti_writefn, s);
- omap_l4_attach(ta, 0, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_sti_ops, s, "omap.sti",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach(ta, 0, &s->iomem);
- iomemtype = cpu_register_io_memory(omap_sti_fifo_readfn,
- omap_sti_fifo_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
+ memory_region_init_io(&s->iomem_fifo, &omap_sti_fifo_ops, s,
+ "omap.sti.fifo", 0x10000);
+ memory_region_add_subregion(sysmem, channel_base, &s->iomem_fifo);
return s;
}
struct omap_prcm_s {
qemu_irq irq[3];
struct omap_mpu_state_s *mpu;
+ MemoryRegion iomem0;
+ MemoryRegion iomem1;
uint32_t irqst[3];
uint32_t irqen[3];
/* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
}
-static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_prcm_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
uint32_t ret;
+ if (size != 4) {
+ return omap_badwidth_read32(opaque, addr);
+ }
+
switch (addr) {
case 0x000: /* PRCM_REVISION */
return 0x10;
}
}
-static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_prcm_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
+ if (size != 4) {
+ return omap_badwidth_write32(opaque, addr, value);
+ }
+
switch (addr) {
case 0x000: /* PRCM_REVISION */
case 0x054: /* PRCM_VOLTST */
case 0x500: /* CM_CLKEN_PLL */
if (value & 0xffffff30)
fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
- "future compatiblity\n", __FUNCTION__);
+ "future compatibility\n", __FUNCTION__);
if ((s->clken[9] ^ value) & 0xcc) {
s->clken[9] &= ~0xcc;
s->clken[9] |= value & 0xcc;
case 0x540: /* CM_CLKSEL1_PLL */
if (value & 0xfc4000d7)
fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
- "future compatiblity\n", __FUNCTION__);
+ "future compatibility\n", __FUNCTION__);
if ((s->clksel[5] ^ value) & 0x003fff00) {
s->clksel[5] = value & 0x03bfff28;
omap_prcm_dpll_update(s);
case 0x544: /* CM_CLKSEL2_PLL */
if (value & ~3)
fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
- "future compatiblity\n", __FUNCTION__);
+ "future compatibility\n", __FUNCTION__);
if (s->clksel[6] != (value & 3)) {
s->clksel[6] = value & 3;
omap_prcm_dpll_update(s);
}
}
-static CPUReadMemoryFunc * const omap_prcm_readfn[] = {
- omap_badwidth_read32,
- omap_badwidth_read32,
- omap_prcm_read,
-};
-
-static CPUWriteMemoryFunc * const omap_prcm_writefn[] = {
- omap_badwidth_write32,
- omap_badwidth_write32,
- omap_prcm_write,
+static const MemoryRegionOps omap_prcm_ops = {
+ .read = omap_prcm_read,
+ .write = omap_prcm_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_prcm_reset(struct omap_prcm_s *s)
qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
struct omap_mpu_state_s *mpu)
{
- int iomemtype;
struct omap_prcm_s *s = (struct omap_prcm_s *)
- qemu_mallocz(sizeof(struct omap_prcm_s));
+ g_malloc0(sizeof(struct omap_prcm_s));
s->irq[0] = mpu_int;
s->irq[1] = dsp_int;
s->mpu = mpu;
omap_prcm_coldreset(s);
- iomemtype = l4_register_io_memory(omap_prcm_readfn,
- omap_prcm_writefn, s);
- omap_l4_attach(ta, 0, iomemtype);
- omap_l4_attach(ta, 1, iomemtype);
+ memory_region_init_io(&s->iomem0, &omap_prcm_ops, s, "omap.pcrm0",
+ omap_l4_region_size(ta, 0));
+ memory_region_init_io(&s->iomem1, &omap_prcm_ops, s, "omap.pcrm1",
+ omap_l4_region_size(ta, 1));
+ omap_l4_attach(ta, 0, &s->iomem0);
+ omap_l4_attach(ta, 1, &s->iomem1);
return s;
}
/* System and Pinout control */
struct omap_sysctl_s {
struct omap_mpu_state_s *mpu;
+ MemoryRegion iomem;
uint32_t sysconfig;
uint32_t devconfig;
uint32_t msuspendmux[5];
};
-static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read8(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
return 0;
}
-static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
+static uint32_t omap_sysctl_read(void *opaque, hwaddr addr)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
return 0;
}
-static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write8(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
}
}
-static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
+static void omap_sysctl_write(void *opaque, hwaddr addr,
uint32_t value)
{
struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
}
}
-static CPUReadMemoryFunc * const omap_sysctl_readfn[] = {
- omap_sysctl_read8,
- omap_badwidth_read32, /* TODO */
- omap_sysctl_read,
-};
-
-static CPUWriteMemoryFunc * const omap_sysctl_writefn[] = {
- omap_sysctl_write8,
- omap_badwidth_write32, /* TODO */
- omap_sysctl_write,
+static const MemoryRegionOps omap_sysctl_ops = {
+ .old_mmio = {
+ .read = {
+ omap_sysctl_read8,
+ omap_badwidth_read32, /* TODO */
+ omap_sysctl_read,
+ },
+ .write = {
+ omap_sysctl_write8,
+ omap_badwidth_write32, /* TODO */
+ omap_sysctl_write,
+ },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_sysctl_reset(struct omap_sysctl_s *s)
static struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
omap_clk iclk, struct omap_mpu_state_s *mpu)
{
- int iomemtype;
struct omap_sysctl_s *s = (struct omap_sysctl_s *)
- qemu_mallocz(sizeof(struct omap_sysctl_s));
+ g_malloc0(sizeof(struct omap_sysctl_s));
s->mpu = mpu;
omap_sysctl_reset(s);
- iomemtype = l4_register_io_memory(omap_sysctl_readfn,
- omap_sysctl_writefn, s);
- omap_l4_attach(ta, 0, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_sysctl_ops, s, "omap.sysctl",
+ omap_l4_region_size(ta, 0));
+ omap_l4_attach(ta, 0, &s->iomem);
return s;
}
{
struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
- omap_inth_reset(mpu->ih[0]);
omap_dma_reset(mpu->dma);
omap_prcm_reset(mpu->prcm);
omap_sysctl_reset(mpu->sysc);
omap_mmc_reset(mpu->mmc);
omap_mcspi_reset(mpu->mcspi[0]);
omap_mcspi_reset(mpu->mcspi[1]);
- omap_i2c_reset(mpu->i2c[0]);
- omap_i2c_reset(mpu->i2c[1]);
- cpu_reset(mpu->env);
+ cpu_reset(CPU(mpu->cpu));
}
static int omap2_validate_addr(struct omap_mpu_state_s *s,
- target_phys_addr_t addr)
+ hwaddr addr)
{
return 1;
}
{ 0, OMAP_INT_24XX_SDMA_IRQ3 },
};
-struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
+struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
+ unsigned long sdram_size,
const char *core)
{
struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
- qemu_mallocz(sizeof(struct omap_mpu_state_s));
- ram_addr_t sram_base, q2_base;
+ g_malloc0(sizeof(struct omap_mpu_state_s));
qemu_irq *cpu_irq;
qemu_irq dma_irqs[4];
DriveInfo *dinfo;
/* Core */
s->mpu_model = omap2420;
- s->env = cpu_init(core ?: "arm1136-r2");
- if (!s->env) {
+ s->cpu = cpu_arm_init(core ?: "arm1136-r2");
+ if (s->cpu == NULL) {
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
omap_clk_init(s);
/* Memory-mapped stuff */
- cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
- (q2_base = qemu_ram_alloc(NULL, "omap2.dram",
- s->sdram_size)) | IO_MEM_RAM);
- cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
- (sram_base = qemu_ram_alloc(NULL, "omap2.sram",
- s->sram_size)) | IO_MEM_RAM);
+ memory_region_init_ram(&s->sdram, "omap2.dram", s->sdram_size);
+ vmstate_register_ram_global(&s->sdram);
+ memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram);
+ memory_region_init_ram(&s->sram, "omap2.sram", s->sram_size);
+ vmstate_register_ram_global(&s->sram);
+ memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram);
- s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
+ s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54);
/* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
- cpu_irq = arm_pic_init_cpu(s->env);
- s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
- cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
- omap_findclk(s, "mpu_intc_fclk"),
- omap_findclk(s, "mpu_intc_iclk"));
-
+ cpu_irq = arm_pic_init_cpu(s->cpu);
+ s->ih[0] = qdev_create(NULL, "omap2-intc");
+ qdev_prop_set_uint8(s->ih[0], "revision", 0x21);
+ qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk"));
+ qdev_prop_set_ptr(s->ih[0], "iclk", omap_findclk(s, "mpu_intc_iclk"));
+ qdev_init_nofail(s->ih[0]);
+ busdev = sysbus_from_qdev(s->ih[0]);
+ sysbus_connect_irq(busdev, 0, cpu_irq[ARM_PIC_CPU_IRQ]);
+ sysbus_connect_irq(busdev, 1, cpu_irq[ARM_PIC_CPU_FIQ]);
+ sysbus_mmio_map(busdev, 0, 0x480fe000);
s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
- s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_PRCM_MPU_IRQ),
+ NULL, NULL, s);
s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
omap_findclk(s, "omapctrl_iclk"), s);
- for (i = 0; i < 4; i ++)
- dma_irqs[i] =
- s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
- s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
+ for (i = 0; i < 4; i++) {
+ dma_irqs[i] = qdev_get_gpio_in(s->ih[omap2_dma_irq_map[i].ih],
+ omap2_dma_irq_map[i].intr);
+ }
+ s->dma = omap_dma4_init(0x48056000, dma_irqs, sysmem, s, 256, 32,
omap_findclk(s, "sdma_iclk"),
omap_findclk(s, "sdma_fclk"));
s->port->addr_valid = omap2_validate_addr;
/* Register SDRAM and SRAM ports for fast DMA transfers. */
- soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
- soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
-
- s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
- s->irq[0][OMAP_INT_24XX_UART1_IRQ],
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sdram),
+ OMAP2_Q2_BASE, s->sdram_size);
+ soc_dma_port_add_mem(s->dma, memory_region_get_ram_ptr(&s->sram),
+ OMAP2_SRAM_BASE, s->sram_size);
+
+ s->uart[0] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 19),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART1_IRQ),
omap_findclk(s, "uart1_fclk"),
omap_findclk(s, "uart1_iclk"),
s->drq[OMAP24XX_DMA_UART1_TX],
s->drq[OMAP24XX_DMA_UART1_RX],
"uart1",
serial_hds[0]);
- s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
- s->irq[0][OMAP_INT_24XX_UART2_IRQ],
+ s->uart[1] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 20),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART2_IRQ),
omap_findclk(s, "uart2_fclk"),
omap_findclk(s, "uart2_iclk"),
s->drq[OMAP24XX_DMA_UART2_TX],
s->drq[OMAP24XX_DMA_UART2_RX],
"uart2",
serial_hds[0] ? serial_hds[1] : NULL);
- s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
- s->irq[0][OMAP_INT_24XX_UART3_IRQ],
+ s->uart[2] = omap2_uart_init(sysmem, omap_l4ta(s->l4, 21),
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_24XX_UART3_IRQ),
omap_findclk(s, "uart3_fclk"),
omap_findclk(s, "uart3_iclk"),
s->drq[OMAP24XX_DMA_UART3_TX],
serial_hds[0] && serial_hds[1] ? serial_hds[2] : NULL);
s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
- s->irq[0][OMAP_INT_24XX_GPTIMER1],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER1),
omap_findclk(s, "wu_gpt1_clk"),
omap_findclk(s, "wu_l4_iclk"));
s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
- s->irq[0][OMAP_INT_24XX_GPTIMER2],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER2),
omap_findclk(s, "core_gpt2_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
- s->irq[0][OMAP_INT_24XX_GPTIMER3],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER3),
omap_findclk(s, "core_gpt3_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
- s->irq[0][OMAP_INT_24XX_GPTIMER4],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER4),
omap_findclk(s, "core_gpt4_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
- s->irq[0][OMAP_INT_24XX_GPTIMER5],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER5),
omap_findclk(s, "core_gpt5_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
- s->irq[0][OMAP_INT_24XX_GPTIMER6],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER6),
omap_findclk(s, "core_gpt6_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
- s->irq[0][OMAP_INT_24XX_GPTIMER7],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER7),
omap_findclk(s, "core_gpt7_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
- s->irq[0][OMAP_INT_24XX_GPTIMER8],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER8),
omap_findclk(s, "core_gpt8_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
- s->irq[0][OMAP_INT_24XX_GPTIMER9],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER9),
omap_findclk(s, "core_gpt9_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
- s->irq[0][OMAP_INT_24XX_GPTIMER10],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER10),
omap_findclk(s, "core_gpt10_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
- s->irq[0][OMAP_INT_24XX_GPTIMER11],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER11),
omap_findclk(s, "core_gpt11_clk"),
omap_findclk(s, "core_l4_iclk"));
s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
- s->irq[0][OMAP_INT_24XX_GPTIMER12],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPTIMER12),
omap_findclk(s, "core_gpt12_clk"),
omap_findclk(s, "core_l4_iclk"));
omap_findclk(s, "clk32-kHz"),
omap_findclk(s, "core_l4_iclk"));
- s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
- s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
- &s->drq[OMAP24XX_DMA_I2C1_TX],
- omap_findclk(s, "i2c1.fclk"),
- omap_findclk(s, "i2c1.iclk"));
- s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
- s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
- &s->drq[OMAP24XX_DMA_I2C2_TX],
- omap_findclk(s, "i2c2.fclk"),
- omap_findclk(s, "i2c2.iclk"));
+ s->i2c[0] = qdev_create(NULL, "omap_i2c");
+ qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
+ qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
+ qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
+ qdev_init_nofail(s->i2c[0]);
+ busdev = sysbus_from_qdev(s->i2c[0]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
+ sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
+ sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
+ sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
+
+ s->i2c[1] = qdev_create(NULL, "omap_i2c");
+ qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
+ qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
+ qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
+ qdev_init_nofail(s->i2c[1]);
+ busdev = sysbus_from_qdev(s->i2c[1]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
+ sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
+ sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
+ sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
s->gpio = qdev_create(NULL, "omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);
}
qdev_init_nofail(s->gpio);
busdev = sysbus_from_qdev(s->gpio);
- sysbus_connect_irq(busdev, 0, s->irq[0][OMAP_INT_24XX_GPIO_BANK1]);
- sysbus_connect_irq(busdev, 3, s->irq[0][OMAP_INT_24XX_GPIO_BANK2]);
- sysbus_connect_irq(busdev, 6, s->irq[0][OMAP_INT_24XX_GPIO_BANK3]);
- sysbus_connect_irq(busdev, 9, s->irq[0][OMAP_INT_24XX_GPIO_BANK4]);
+ sysbus_connect_irq(busdev, 0,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK1));
+ sysbus_connect_irq(busdev, 3,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK2));
+ sysbus_connect_irq(busdev, 6,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK3));
+ sysbus_connect_irq(busdev, 9,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPIO_BANK4));
+ if (s->mpu_model == omap2430) {
+ sysbus_connect_irq(busdev, 12,
+ qdev_get_gpio_in(s->ih[0],
+ OMAP_INT_243X_GPIO_BANK5));
+ }
ta = omap_l4ta(s->l4, 3);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(ta, 1));
sysbus_mmio_map(busdev, 1, omap_l4_region_base(ta, 0));
sysbus_mmio_map(busdev, 3, omap_l4_region_base(ta, 4));
sysbus_mmio_map(busdev, 4, omap_l4_region_base(ta, 5));
- s->sdrc = omap_sdrc_init(0x68009000);
- s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
+ s->sdrc = omap_sdrc_init(sysmem, 0x68009000);
+ s->gpmc = omap_gpmc_init(s, 0x6800a000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_GPMC_IRQ),
+ s->drq[OMAP24XX_DMA_GPMC]);
dinfo = drive_get(IF_SD, 0, 0);
if (!dinfo) {
exit(1);
}
s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), dinfo->bdrv,
- s->irq[0][OMAP_INT_24XX_MMC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MMC_IRQ),
&s->drq[OMAP24XX_DMA_MMC1_TX],
omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
- s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI1_IRQ),
&s->drq[OMAP24XX_DMA_SPI1_TX0],
omap_findclk(s, "spi1_fclk"),
omap_findclk(s, "spi1_iclk"));
s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
- s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_MCSPI2_IRQ),
&s->drq[OMAP24XX_DMA_SPI2_TX0],
omap_findclk(s, "spi2_fclk"),
omap_findclk(s, "spi2_iclk"));
- s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
+ s->dss = omap_dss_init(omap_l4ta(s->l4, 10), sysmem, 0x68000800,
/* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
- s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_DSS_IRQ),
+ s->drq[OMAP24XX_DMA_DSS],
omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
omap_findclk(s, "dss_54m_clk"),
omap_findclk(s, "dss_l3_iclk"),
omap_findclk(s, "dss_l4_iclk"));
- omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
- s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
+ omap_sti_init(omap_l4ta(s->l4, 18), sysmem, 0x54000000,
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_STI),
+ omap_findclk(s, "emul_ck"),
serial_hds[0] && serial_hds[1] && serial_hds[2] ?
serial_hds[3] : NULL);
s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
- s->irq[0][OMAP_INT_24XX_EAC_IRQ],
+ qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_EAC_IRQ),
/* Ten consecutive lines */
&s->drq[OMAP24XX_DMA_EAC_AC_RD],
omap_findclk(s, "func_96m_clk"),
projects / qemu.git / blobdiff