* with this program; if not, see <http://www.gnu.org/licenses/>.
*/
#include "qemu-common.h"
-#include "qemu-timer.h"
+#include "qemu/timer.h"
#include "omap.h"
#include "irq.h"
#include "soc_dma.h"
int endian_lock[2];
int translate[2];
enum omap_dma_port port[2];
- target_phys_addr_t addr[2];
+ hwaddr addr[2];
omap_dma_addressing_t mode[2];
uint32_t elements;
uint16_t frames;
struct omap_dma_channel_s *sibling;
struct omap_dma_reg_set_s {
- target_phys_addr_t src, dest;
+ hwaddr src, dest;
int frame;
int element;
int pck_element;
struct omap_dma_s {
struct soc_dma_s *dma;
+ MemoryRegion iomem;
struct omap_mpu_state_s *mpu;
omap_clk clk;
break;
case 0x06: /* SYS_DMA_CSR_CH0 */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x08: /* SYS_DMA_CSSA_L_CH0 */
break;
case 0x18: /* SYS_DMA_CPC_CH0 or DMA_CSAC */
- OMAP_RO_REG((target_phys_addr_t) reg);
+ OMAP_RO_REG((hwaddr) reg);
break;
case 0x1c: /* DMA_CDEI */
return 0;
}
-static uint32_t omap_dma_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_dma_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
uint16_t ret;
+ if (size != 2) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
return 0;
}
-static void omap_dma_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_dma_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int reg, ch;
+ if (size != 2) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x300 ... 0x3fe:
if (s->model <= omap_dma_3_1 || !s->omap_3_1_mapping_disabled) {
OMAP_BAD_REG(addr);
}
-static CPUReadMemoryFunc * const omap_dma_readfn[] = {
- omap_badwidth_read16,
- omap_dma_read,
- omap_badwidth_read16,
-};
-
-static CPUWriteMemoryFunc * const omap_dma_writefn[] = {
- omap_badwidth_write16,
- omap_dma_write,
- omap_badwidth_write16,
+static const MemoryRegionOps omap_dma_ops = {
+ .read = omap_dma_read,
+ .write = omap_dma_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void omap_dma_request(void *opaque, int drq, int req)
}
}
-struct soc_dma_s *omap_dma_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma_init(hwaddr base, qemu_irq *irqs,
+ MemoryRegion *sysmem,
qemu_irq lcd_irq, struct omap_mpu_state_s *mpu, omap_clk clk,
enum omap_dma_model model)
{
- int iomemtype, num_irqs, memsize, i;
+ int num_irqs, memsize, i;
struct omap_dma_s *s = (struct omap_dma_s *)
g_malloc0(sizeof(struct omap_dma_s));
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, 1);
- iomemtype = cpu_register_io_memory(omap_dma_readfn,
- omap_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, memsize, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_dma_ops, s, "omap.dma", memsize);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;
qemu_irq_raise(s->irq[3]);
}
-static uint32_t omap_dma4_read(void *opaque, target_phys_addr_t addr)
+static uint64_t omap_dma4_read(void *opaque, hwaddr addr,
+ unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int irqn = 0, chnum;
struct omap_dma_channel_s *ch;
+ if (size == 1) {
+ return omap_badwidth_read16(opaque, addr);
+ }
+
switch (addr) {
case 0x00: /* DMA4_REVISION */
return 0x40;
}
}
-static void omap_dma4_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void omap_dma4_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
struct omap_dma_s *s = (struct omap_dma_s *) opaque;
int chnum, irqn = 0;
struct omap_dma_channel_s *ch;
+ if (size == 1) {
+ return omap_badwidth_write16(opaque, addr, value);
+ }
+
switch (addr) {
case 0x14: /* DMA4_IRQSTATUS_L3 */
irqn ++;
break;
case 0x1c: /* DMA4_CSSA */
- ch->addr[0] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[0] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
case 0x20: /* DMA4_CDSA */
- ch->addr[1] = (target_phys_addr_t) (uint32_t) value;
+ ch->addr[1] = (hwaddr) (uint32_t) value;
ch->set_update = 1;
break;
}
}
-static CPUReadMemoryFunc * const omap_dma4_readfn[] = {
- omap_badwidth_read16,
- omap_dma4_read,
- omap_dma4_read,
+static const MemoryRegionOps omap_dma4_ops = {
+ .read = omap_dma4_read,
+ .write = omap_dma4_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const omap_dma4_writefn[] = {
- omap_badwidth_write16,
- omap_dma4_write,
- omap_dma4_write,
-};
-
-struct soc_dma_s *omap_dma4_init(target_phys_addr_t base, qemu_irq *irqs,
+struct soc_dma_s *omap_dma4_init(hwaddr base, qemu_irq *irqs,
+ MemoryRegion *sysmem,
struct omap_mpu_state_s *mpu, int fifo,
int chans, omap_clk iclk, omap_clk fclk)
{
- int iomemtype, i;
+ int i;
struct omap_dma_s *s = (struct omap_dma_s *)
g_malloc0(sizeof(struct omap_dma_s));
omap_dma_reset(s->dma);
omap_dma_clk_update(s, 0, !!s->dma->freq);
- iomemtype = cpu_register_io_memory(omap_dma4_readfn,
- omap_dma4_writefn, s, DEVICE_NATIVE_ENDIAN);
- cpu_register_physical_memory(base, 0x1000, iomemtype);
+ memory_region_init_io(&s->iomem, &omap_dma4_ops, s, "omap.dma4", 0x1000);
+ memory_region_add_subregion(sysmem, base, &s->iomem);
mpu->drq = s->dma->drq;