#include "hw.h"
#include "flash.h"
#include "irq.h"
-#include "blockdev.h"
+#include "sysemu/blockdev.h"
+#include "exec/memory.h"
+#include "exec/address-spaces.h"
+#include "sysbus.h"
+#include "qemu/error-report.h"
/* 11 for 2kB-page OneNAND ("2nd generation") and 10 for 1kB-page chips */
#define PAGE_SHIFT 11
#define BLOCK_SHIFT (PAGE_SHIFT + 6)
typedef struct {
+ SysBusDevice busdev;
struct {
uint16_t man;
uint16_t dev;
uint16_t ver;
} id;
int shift;
- target_phys_addr_t base;
+ hwaddr base;
qemu_irq intr;
qemu_irq rdy;
BlockDriverState *bdrv;
uint8_t *image;
uint8_t *otp;
uint8_t *current;
- ram_addr_t ram;
+ MemoryRegion ram;
+ MemoryRegion mapped_ram;
+ uint8_t current_direction;
uint8_t *boot[2];
uint8_t *data[2][2];
- int iomemtype;
+ MemoryRegion iomem;
+ MemoryRegion container;
int cycle;
int otpmode;
ONEN_LOCK_UNLOCKED = 1 << 2,
};
-void onenand_base_update(void *opaque, target_phys_addr_t new)
+static void onenand_mem_setup(OneNANDState *s)
{
- OneNANDState *s = (OneNANDState *) opaque;
-
- s->base = new;
-
/* XXX: We should use IO_MEM_ROMD but we broke it earlier...
* Both 0x0000 ... 0x01ff and 0x8000 ... 0x800f can be used to
* write boot commands. Also take note of the BWPS bit. */
- cpu_register_physical_memory(s->base + (0x0000 << s->shift),
- 0x0200 << s->shift, s->iomemtype);
- cpu_register_physical_memory(s->base + (0x0200 << s->shift),
- 0xbe00 << s->shift,
- (s->ram +(0x0200 << s->shift)) | IO_MEM_RAM);
- if (s->iomemtype)
- cpu_register_physical_memory_offset(s->base + (0xc000 << s->shift),
- 0x4000 << s->shift, s->iomemtype, (0xc000 << s->shift));
+ memory_region_init(&s->container, "onenand", 0x10000 << s->shift);
+ memory_region_add_subregion(&s->container, 0, &s->iomem);
+ memory_region_init_alias(&s->mapped_ram, "onenand-mapped-ram",
+ &s->ram, 0x0200 << s->shift,
+ 0xbe00 << s->shift);
+ memory_region_add_subregion_overlap(&s->container,
+ 0x0200 << s->shift,
+ &s->mapped_ram,
+ 1);
}
-void onenand_base_unmap(void *opaque)
+static void onenand_intr_update(OneNANDState *s)
{
- OneNANDState *s = (OneNANDState *) opaque;
+ qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
+}
- cpu_register_physical_memory(s->base,
- 0x10000 << s->shift, IO_MEM_UNASSIGNED);
+static void onenand_pre_save(void *opaque)
+{
+ OneNANDState *s = opaque;
+ if (s->current == s->otp) {
+ s->current_direction = 1;
+ } else if (s->current == s->image) {
+ s->current_direction = 2;
+ } else {
+ s->current_direction = 0;
+ }
}
-static void onenand_intr_update(OneNANDState *s)
+static int onenand_post_load(void *opaque, int version_id)
{
- qemu_set_irq(s->intr, ((s->intstatus >> 15) ^ (~s->config[0] >> 6)) & 1);
+ OneNANDState *s = opaque;
+ switch (s->current_direction) {
+ case 0:
+ break;
+ case 1:
+ s->current = s->otp;
+ break;
+ case 2:
+ s->current = s->image;
+ break;
+ default:
+ return -1;
+ }
+ onenand_intr_update(s);
+ return 0;
}
+static const VMStateDescription vmstate_onenand = {
+ .name = "onenand",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .pre_save = onenand_pre_save,
+ .post_load = onenand_post_load,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT8(current_direction, OneNANDState),
+ VMSTATE_INT32(cycle, OneNANDState),
+ VMSTATE_INT32(otpmode, OneNANDState),
+ VMSTATE_UINT16_ARRAY(addr, OneNANDState, 8),
+ VMSTATE_UINT16_ARRAY(unladdr, OneNANDState, 8),
+ VMSTATE_INT32(bufaddr, OneNANDState),
+ VMSTATE_INT32(count, OneNANDState),
+ VMSTATE_UINT16(command, OneNANDState),
+ VMSTATE_UINT16_ARRAY(config, OneNANDState, 2),
+ VMSTATE_UINT16(status, OneNANDState),
+ VMSTATE_UINT16(intstatus, OneNANDState),
+ VMSTATE_UINT16(wpstatus, OneNANDState),
+ VMSTATE_INT32(secs_cur, OneNANDState),
+ VMSTATE_PARTIAL_VBUFFER(blockwp, OneNANDState, blocks),
+ VMSTATE_UINT8(ecc.cp, OneNANDState),
+ VMSTATE_UINT16_ARRAY(ecc.lp, OneNANDState, 2),
+ VMSTATE_UINT16(ecc.count, OneNANDState),
+ VMSTATE_BUFFER_UNSAFE(otp, OneNANDState, 0, ((64 + 2) << PAGE_SHIFT)),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
/* Hot reset (Reset OneNAND command) or warm reset (RP pin low) */
static void onenand_reset(OneNANDState *s, int cold)
{
/* Lock the whole flash */
memset(s->blockwp, ONEN_LOCK_LOCKED, s->blocks);
- if (s->bdrv && bdrv_read(s->bdrv, 0, s->boot[0], 8) < 0)
- hw_error("%s: Loading the BootRAM failed.\n", __FUNCTION__);
+ if (s->bdrv_cur && bdrv_read(s->bdrv_cur, 0, s->boot[0], 8) < 0) {
+ hw_error("%s: Loading the BootRAM failed.\n", __func__);
+ }
}
}
+static void onenand_system_reset(DeviceState *dev)
+{
+ onenand_reset(FROM_SYSBUS(OneNANDState, sysbus_from_qdev(dev)), 1);
+}
+
static inline int onenand_load_main(OneNANDState *s, int sec, int secn,
void *dest)
{
int result = 0;
if (secn > 0) {
- uint32_t size = (uint32_t) secn * 512;
- const uint8_t *sp = (const uint8_t *) src;
+ uint32_t size = (uint32_t)secn * 512;
+ const uint8_t *sp = (const uint8_t *)src;
uint8_t *dp = 0;
if (s->bdrv_cur) {
- dp = qemu_malloc(size);
+ dp = g_malloc(size);
if (!dp || bdrv_read(s->bdrv_cur, sec, dp, secn) < 0) {
result = 1;
}
if (sec + secn > s->secs_cur) {
result = 1;
} else {
- dp = (uint8_t *) s->current + (sec << 9);
+ dp = (uint8_t *)s->current + (sec << 9);
}
}
if (!result) {
}
}
if (dp && s->bdrv_cur) {
- qemu_free(dp);
+ g_free(dp);
}
}
{
int result = 0;
if (secn > 0) {
- const uint8_t *sp = (const uint8_t *) src;
+ const uint8_t *sp = (const uint8_t *)src;
uint8_t *dp = 0, *dpp = 0;
if (s->bdrv_cur) {
- dp = qemu_malloc(512);
+ dp = g_malloc(512);
if (!dp || bdrv_read(s->bdrv_cur,
- s->secs_cur + (sec >> 5),
- dp, 1) < 0) {
+ s->secs_cur + (sec >> 5),
+ dp, 1) < 0) {
result = 1;
} else {
dpp = dp + ((sec & 31) << 4);
}
if (s->bdrv_cur) {
result = bdrv_write(s->bdrv_cur, s->secs_cur + (sec >> 5),
- dp, 1) < 0;
+ dp, 1) < 0;
}
}
if (dp) {
- qemu_free(dp);
+ g_free(dp);
}
}
return result;
static inline int onenand_erase(OneNANDState *s, int sec, int num)
{
uint8_t *blankbuf, *tmpbuf;
- blankbuf = qemu_malloc(512);
+ blankbuf = g_malloc(512);
if (!blankbuf) {
return 1;
}
- tmpbuf = qemu_malloc(512);
+ tmpbuf = g_malloc(512);
if (!tmpbuf) {
- qemu_free(blankbuf);
+ g_free(blankbuf);
return 1;
}
memset(blankbuf, 0xff, 512);
for (; num > 0; num--, sec++) {
if (s->bdrv_cur) {
int erasesec = s->secs_cur + (sec >> 5);
- if (bdrv_write(s->bdrv_cur, sec, blankbuf, 1)) {
+ if (bdrv_write(s->bdrv_cur, sec, blankbuf, 1) < 0) {
goto fail;
}
if (bdrv_read(s->bdrv_cur, erasesec, tmpbuf, 1) < 0) {
}
}
- qemu_free(tmpbuf);
- qemu_free(blankbuf);
+ g_free(tmpbuf);
+ g_free(blankbuf);
return 0;
fail:
- qemu_free(tmpbuf);
- qemu_free(blankbuf);
+ g_free(tmpbuf);
+ g_free(blankbuf);
return 1;
}
-static void onenand_command(OneNANDState *s, int cmd)
+static void onenand_command(OneNANDState *s)
{
int b;
int sec;
s->data[(s->bufaddr >> 2) & 1][1] : s->boot[1]; \
buf += (s->bufaddr & 3) << 4;
- switch (cmd) {
+ switch (s->command) {
case 0x00: /* Load single/multiple sector data unit into buffer */
SETADDR(ONEN_BUF_BLOCK, ONEN_BUF_PAGE)
s->status |= ONEN_ERR_CMD;
s->intstatus |= ONEN_INT;
fprintf(stderr, "%s: unknown OneNAND command %x\n",
- __FUNCTION__, cmd);
+ __func__, s->command);
}
onenand_intr_update(s);
}
-static uint32_t onenand_read(void *opaque, target_phys_addr_t addr)
+static uint64_t onenand_read(void *opaque, hwaddr addr,
+ unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
return 0;
}
-static void onenand_write(void *opaque, target_phys_addr_t addr,
- uint32_t value)
+static void onenand_write(void *opaque, hwaddr addr,
+ uint64_t value, unsigned size)
{
OneNANDState *s = (OneNANDState *) opaque;
int offset = addr >> s->shift;
break;
default:
- fprintf(stderr, "%s: unknown OneNAND boot command %x\n",
+ fprintf(stderr, "%s: unknown OneNAND boot command %"PRIx64"\n",
__FUNCTION__, value);
}
break;
if (s->intstatus & (1 << 15))
break;
s->command = value;
- onenand_command(s, s->command);
+ onenand_command(s);
break;
case 0xf221: /* System Configuration 1 */
s->config[0] = value;
}
}
-static CPUReadMemoryFunc * const onenand_readfn[] = {
- onenand_read, /* TODO */
- onenand_read,
- onenand_read,
+static const MemoryRegionOps onenand_ops = {
+ .read = onenand_read,
+ .write = onenand_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc * const onenand_writefn[] = {
- onenand_write, /* TODO */
- onenand_write,
- onenand_write,
-};
-
-void *onenand_init(BlockDriverState *bdrv,
- uint16_t man_id, uint16_t dev_id, uint16_t ver_id,
- int regshift, qemu_irq irq)
+static int onenand_initfn(SysBusDevice *dev)
{
- OneNANDState *s = (OneNANDState *) qemu_mallocz(sizeof(*s));
- uint32_t size = 1 << (24 + ((dev_id >> 4) & 7));
+ OneNANDState *s = (OneNANDState *)dev;
+ uint32_t size = 1 << (24 + ((s->id.dev >> 4) & 7));
void *ram;
-
- s->shift = regshift;
- s->intr = irq;
+ s->base = (hwaddr)-1;
s->rdy = NULL;
- s->id.man = man_id;
- s->id.dev = dev_id;
- s->id.ver = ver_id;
s->blocks = size >> BLOCK_SHIFT;
s->secs = size >> 9;
- s->blockwp = qemu_malloc(s->blocks);
- s->density_mask = (dev_id & 0x08) ? (1 << (6 + ((dev_id >> 4) & 7))) : 0;
- s->iomemtype = cpu_register_io_memory(onenand_readfn,
- onenand_writefn, s, DEVICE_NATIVE_ENDIAN);
- s->bdrv = bdrv;
+ s->blockwp = g_malloc(s->blocks);
+ s->density_mask = (s->id.dev & 0x08)
+ ? (1 << (6 + ((s->id.dev >> 4) & 7))) : 0;
+ memory_region_init_io(&s->iomem, &onenand_ops, s, "onenand",
+ 0x10000 << s->shift);
if (!s->bdrv) {
- s->image = memset(qemu_malloc(size + (size >> 5)),
- 0xff, size + (size >> 5));
+ s->image = memset(g_malloc(size + (size >> 5)),
+ 0xff, size + (size >> 5));
+ } else {
+ if (bdrv_is_read_only(s->bdrv)) {
+ error_report("Can't use a read-only drive");
+ return -1;
+ }
+ s->bdrv_cur = s->bdrv;
}
- s->otp = memset(qemu_malloc((64 + 2) << PAGE_SHIFT),
+ s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT),
0xff, (64 + 2) << PAGE_SHIFT);
- s->ram = qemu_ram_alloc(NULL, "onenand.ram", 0xc000 << s->shift);
- ram = qemu_get_ram_ptr(s->ram);
+ memory_region_init_ram(&s->ram, "onenand.ram", 0xc000 << s->shift);
+ vmstate_register_ram_global(&s->ram);
+ ram = memory_region_get_ram_ptr(&s->ram);
s->boot[0] = ram + (0x0000 << s->shift);
s->boot[1] = ram + (0x8000 << s->shift);
s->data[0][0] = ram + ((0x0200 + (0 << (PAGE_SHIFT - 1))) << s->shift);
s->data[0][1] = ram + ((0x8010 + (0 << (PAGE_SHIFT - 6))) << s->shift);
s->data[1][0] = ram + ((0x0200 + (1 << (PAGE_SHIFT - 1))) << s->shift);
s->data[1][1] = ram + ((0x8010 + (1 << (PAGE_SHIFT - 6))) << s->shift);
+ onenand_mem_setup(s);
+ sysbus_init_irq(dev, &s->intr);
+ sysbus_init_mmio(dev, &s->container);
+ vmstate_register(&dev->qdev,
+ ((s->shift & 0x7f) << 24)
+ | ((s->id.man & 0xff) << 16)
+ | ((s->id.dev & 0xff) << 8)
+ | (s->id.ver & 0xff),
+ &vmstate_onenand, s);
+ return 0;
+}
- onenand_reset(s, 1);
+static Property onenand_properties[] = {
+ DEFINE_PROP_UINT16("manufacturer_id", OneNANDState, id.man, 0),
+ DEFINE_PROP_UINT16("device_id", OneNANDState, id.dev, 0),
+ DEFINE_PROP_UINT16("version_id", OneNANDState, id.ver, 0),
+ DEFINE_PROP_INT32("shift", OneNANDState, shift, 0),
+ DEFINE_PROP_DRIVE("drive", OneNANDState, bdrv),
+ DEFINE_PROP_END_OF_LIST(),
+};
- return s;
+static void onenand_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = onenand_initfn;
+ dc->reset = onenand_system_reset;
+ dc->props = onenand_properties;
}
-void *onenand_raw_otp(void *opaque)
+static TypeInfo onenand_info = {
+ .name = "onenand",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(OneNANDState),
+ .class_init = onenand_class_init,
+};
+
+static void onenand_register_types(void)
{
- OneNANDState *s = (OneNANDState *) opaque;
+ type_register_static(&onenand_info);
+}
- return s->otp;
+void *onenand_raw_otp(DeviceState *onenand_device)
+{
+ return FROM_SYSBUS(OneNANDState, sysbus_from_qdev(onenand_device))->otp;
}
+
+type_init(onenand_register_types)
projects / qemu.git / blobdiff