int max_irq;
int irq_ipi0;
int irq_tim0;
- int need_swap;
void (*reset) (void *);
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
-static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
-{
- if (opp->need_swap)
- return bswap32(val);
-
- return val;
-}
-
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q->queue, n_IRQ);
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- val = openpic_swap32(opp, val);
addr &= 0xFF;
switch (addr) {
case 0x00: /* FREP */
break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
- retval = openpic_swap32(opp, retval);
return retval;
}
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- val = openpic_swap32(opp, val);
addr -= 0x1100;
addr &= 0xFFFF;
idx = (addr & 0xFFF0) >> 6;
break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
- retval = openpic_swap32(opp, retval);
return retval;
}
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- val = openpic_swap32(opp, val);
addr = addr & 0xFFF0;
idx = addr >> 5;
if (addr & 0x10) {
retval = read_IRQreg(opp, idx, IRQ_IPVP);
}
DPRINTF("%s: => %08x\n", __func__, retval);
- retval = openpic_swap32(opp, retval);
return retval;
}
DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- val = openpic_swap32(opp, val);
addr &= 0x1FFF0;
idx = addr / 0x1000;
dst = &opp->dst[idx];
break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
- retval = openpic_swap32(opp, retval);
return retval;
}
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
opp_io_memory = cpu_register_io_memory(openpic_src_read,
- openpic_src_write);
+ openpic_src_write, NULL
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
- pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
pci_conf[0x3d] = 0x00; // no interrupt pin
/* Register I/O spaces */
- pci_register_bar((PCIDevice *)opp, 0, 0x40000,
+ pci_register_bar(&opp->pci_dev, 0, 0x40000,
PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map);
} else {
opp = qemu_mallocz(sizeof(openpic_t));
}
- opp->mem_index = cpu_register_io_memory(openpic_read,
- openpic_write, opp);
+ opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
+ DEVICE_LITTLE_ENDIAN);
// isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus;
for (i = 0; i < nb_cpus; i++)
opp->dst[i].irqs = irqs[i];
opp->irq_out = irq_out;
- opp->need_swap = 1;
register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
openpic_save, openpic_load, opp);
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
- mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp);
+ mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
+ DEVICE_BIG_ENDIAN);
if (mem_index < 0) {
goto free;
}
for (i = 0; i < nb_cpus; i++)
mpp->dst[i].irqs = irqs[i];
mpp->irq_out = irq_out;
- mpp->need_swap = 0; /* MPIC has the same endian as target */
mpp->irq_raise = mpic_irq_raise;
mpp->reset = mpic_reset;