//#define DEBUG_OPENPIC
#ifdef DEBUG_OPENPIC
-#define DPRINTF(fmt, args...) do { printf(fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...) do { printf(fmt , ## __VA_ARGS__); } while (0)
#else
-#define DPRINTF(fmt, args...) do { } while (0)
+#define DPRINTF(fmt, ...) do { } while (0)
#endif
-#define ERROR(fmr, args...) do { printf("ERROR: " fmr , ##args); } while (0)
#define USE_MPCxxx /* Intel model is broken, for now */
#error "Please select which OpenPic implementation is to be emulated"
#endif
+#define OPENPIC_PAGE_SIZE 4096
+
#define BF_WIDTH(_bits_) \
(((_bits_) + (sizeof(uint32_t) * 8) - 1) / (sizeof(uint32_t) * 8))
int nb_cpus;
/* Timer registers */
struct {
- uint32_t ticc; /* Global timer current count register */
- uint32_t tibc; /* Global timer base count register */
+ uint32_t ticc; /* Global timer current count register */
+ uint32_t tibc; /* Global timer base count register */
} timers[MAX_TMR];
#if MAX_DBL > 0
/* Doorbell registers */
uint32_t dar; /* Doorbell activate register */
struct {
- uint32_t dmr; /* Doorbell messaging register */
+ uint32_t dmr; /* Doorbell messaging register */
} doorbells[MAX_DBL];
#endif
#if MAX_MBX > 0
/* Mailbox registers */
struct {
- uint32_t mbr; /* Mailbox register */
+ uint32_t mbr; /* Mailbox register */
} mailboxes[MAX_MAILBOXES];
#endif
/* IRQ out is used when in bypass mode (not implemented) */
int max_irq;
int irq_ipi0;
int irq_tim0;
- int need_swap;
void (*reset) (void *);
void (*irq_raise) (struct openpic_t *, int, IRQ_src_t *);
} openpic_t;
-static inline uint32_t openpic_swap32(openpic_t *opp, uint32_t val)
-{
- if (opp->need_swap)
- return bswap32(val);
-
- return val;
-}
-
static inline void IRQ_setbit (IRQ_queue_t *q, int n_IRQ)
{
set_bit(q->queue, n_IRQ);
next = -1;
priority = -1;
for (i = 0; i < opp->max_irq; i++) {
- if (IRQ_testbit(q, i)) {
+ if (IRQ_testbit(q, i)) {
DPRINTF("IRQ_check: irq %d set ipvp_pr=%d pr=%d\n",
i, IPVP_PRIORITY(opp->src[i].ipvp), priority);
- if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
- next = i;
- priority = IPVP_PRIORITY(opp->src[i].ipvp);
- }
- }
+ if (IPVP_PRIORITY(opp->src[i].ipvp) > priority) {
+ next = i;
+ priority = IPVP_PRIORITY(opp->src[i].ipvp);
+ }
+ }
}
q->next = next;
q->priority = priority;
{
if (q->next == -1) {
/* XXX: optimize */
- IRQ_check(opp, q);
+ IRQ_check(opp, q);
}
return q->next;
src = &opp->src[n_IRQ];
priority = IPVP_PRIORITY(src->ipvp);
if (priority <= dst->pctp) {
- /* Too low priority */
+ /* Too low priority */
DPRINTF("%s: IRQ %d has too low priority on CPU %d\n",
__func__, n_IRQ, n_CPU);
- return;
+ return;
}
if (IRQ_testbit(&dst->raised, n_IRQ)) {
- /* Interrupt miss */
+ /* Interrupt miss */
DPRINTF("%s: IRQ %d was missed on CPU %d\n",
__func__, n_IRQ, n_CPU);
- return;
+ return;
}
set_bit(&src->ipvp, IPVP_ACTIVITY);
IRQ_setbit(&dst->raised, n_IRQ);
return;
}
if (test_bit(&src->ipvp, IPVP_MASK)) {
- /* Interrupt source is disabled */
+ /* Interrupt source is disabled */
DPRINTF("%s: IRQ %d is disabled\n", __func__, n_IRQ);
- return;
+ return;
}
if (IPVP_PRIORITY(src->ipvp) == 0) {
- /* Priority set to zero */
+ /* Priority set to zero */
DPRINTF("%s: IRQ %d has 0 priority\n", __func__, n_IRQ);
- return;
+ return;
}
if (test_bit(&src->ipvp, IPVP_ACTIVITY)) {
/* IRQ already active */
return;
}
if (src->ide == 0x00000000) {
- /* No target */
+ /* No target */
DPRINTF("%s: IRQ %d has no target\n", __func__, n_IRQ);
- return;
+ return;
}
if (src->ide == (1 << src->last_cpu)) {
opp->micr = 0x00000000;
/* Initialise IRQ sources */
for (i = 0; i < opp->max_irq; i++) {
- opp->src[i].ipvp = 0xA0000000;
- opp->src[i].ide = 0x00000000;
+ opp->src[i].ipvp = 0xA0000000;
+ opp->src[i].ide = 0x00000000;
}
/* Initialise IRQ destinations */
for (i = 0; i < MAX_CPU; i++) {
- opp->dst[i].pctp = 0x0000000F;
- opp->dst[i].pcsr = 0x00000000;
- memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
- memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
+ opp->dst[i].pctp = 0x0000000F;
+ opp->dst[i].pcsr = 0x00000000;
+ memset(&opp->dst[i].raised, 0, sizeof(IRQ_queue_t));
+ opp->dst[i].raised.next = -1;
+ memset(&opp->dst[i].servicing, 0, sizeof(IRQ_queue_t));
+ opp->dst[i].servicing.next = -1;
}
/* Initialise timers */
for (i = 0; i < MAX_TMR; i++) {
- opp->timers[i].ticc = 0x00000000;
- opp->timers[i].tibc = 0x80000000;
+ opp->timers[i].ticc = 0x00000000;
+ opp->timers[i].tibc = 0x80000000;
}
/* Initialise doorbells */
#if MAX_DBL > 0
opp->dar = 0x00000000;
for (i = 0; i < MAX_DBL; i++) {
- opp->doorbells[i].dmr = 0x00000000;
+ opp->doorbells[i].dmr = 0x00000000;
}
#endif
/* Initialise mailboxes */
#if MAX_MBX > 0
for (i = 0; i < MAX_MBX; i++) { /* ? */
- opp->mailboxes[i].mbr = 0x00000000;
+ opp->mailboxes[i].mbr = 0x00000000;
}
#endif
/* Go out of RESET state */
switch (reg) {
case IRQ_IPVP:
- retval = opp->src[n_IRQ].ipvp;
- break;
+ retval = opp->src[n_IRQ].ipvp;
+ break;
case IRQ_IDE:
- retval = opp->src[n_IRQ].ide;
- break;
+ retval = opp->src[n_IRQ].ide;
+ break;
}
return retval;
/* NOTE: not fully accurate for special IRQs, but simple and
sufficient */
/* ACTIVITY bit is read-only */
- opp->src[n_IRQ].ipvp =
+ opp->src[n_IRQ].ipvp =
(opp->src[n_IRQ].ipvp & 0x40000000) |
(val & 0x800F00FF);
openpic_update_irq(opp, n_IRQ);
DPRINTF("Set IPVP %d to 0x%08x -> 0x%08x\n",
n_IRQ, val, opp->src[n_IRQ].ipvp);
- break;
+ break;
case IRQ_IDE:
- tmp = val & 0xC0000000;
+ tmp = val & 0xC0000000;
tmp |= val & ((1 << MAX_CPU) - 1);
- opp->src[n_IRQ].ide = tmp;
+ opp->src[n_IRQ].ide = tmp;
DPRINTF("Set IDE %d to 0x%08x\n", n_IRQ, opp->src[n_IRQ].ide);
- break;
+ break;
}
}
#if 0 // Code provision for Intel model
#if MAX_DBL > 0
static uint32_t read_doorbell_register (openpic_t *opp,
- int n_dbl, uint32_t offset)
+ int n_dbl, uint32_t offset)
{
uint32_t retval;
switch (offset) {
case DBL_IPVP_OFFSET:
- retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
- break;
+ retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP);
+ break;
case DBL_IDE_OFFSET:
- retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
- break;
+ retval = read_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE);
+ break;
case DBL_DMR_OFFSET:
- retval = opp->doorbells[n_dbl].dmr;
- break;
+ retval = opp->doorbells[n_dbl].dmr;
+ break;
}
return retval;
}
static void write_doorbell_register (penpic_t *opp, int n_dbl,
- uint32_t offset, uint32_t value)
+ uint32_t offset, uint32_t value)
{
switch (offset) {
case DBL_IVPR_OFFSET:
- write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
- break;
+ write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IPVP, value);
+ break;
case DBL_IDE_OFFSET:
- write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
- break;
+ write_IRQreg(opp, IRQ_DBL0 + n_dbl, IRQ_IDE, value);
+ break;
case DBL_DMR_OFFSET:
- opp->doorbells[n_dbl].dmr = value;
- break;
+ opp->doorbells[n_dbl].dmr = value;
+ break;
}
}
#endif
#if MAX_MBX > 0
static uint32_t read_mailbox_register (openpic_t *opp,
- int n_mbx, uint32_t offset)
+ int n_mbx, uint32_t offset)
{
uint32_t retval;
switch (offset) {
case MBX_MBR_OFFSET:
- retval = opp->mailboxes[n_mbx].mbr;
- break;
+ retval = opp->mailboxes[n_mbx].mbr;
+ break;
case MBX_IVPR_OFFSET:
- retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
- break;
+ retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP);
+ break;
case MBX_DMR_OFFSET:
- retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
- break;
+ retval = read_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE);
+ break;
}
return retval;
}
static void write_mailbox_register (openpic_t *opp, int n_mbx,
- uint32_t address, uint32_t value)
+ uint32_t address, uint32_t value)
{
switch (offset) {
case MBX_MBR_OFFSET:
- opp->mailboxes[n_mbx].mbr = value;
- break;
+ opp->mailboxes[n_mbx].mbr = value;
+ break;
case MBX_IVPR_OFFSET:
- write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
- break;
+ write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IPVP, value);
+ break;
case MBX_DMR_OFFSET:
- write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
- break;
+ write_IRQreg(opp, IRQ_MBX0 + n_mbx, IRQ_IDE, value);
+ break;
}
}
#endif
IRQ_dst_t *dst;
int idx;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
-#if defined TARGET_WORDS_BIGENDIAN
- val = openpic_swap32(opp, val);
-#endif
addr &= 0xFF;
switch (addr) {
case 0x00: /* FREP */
if (val & 0x80000000 && opp->reset)
opp->reset(opp);
opp->glbc = val & ~0x80000000;
- break;
+ break;
case 0x80: /* VENI */
- break;
+ break;
case 0x90: /* PINT */
for (idx = 0; idx < opp->nb_cpus; idx++) {
if ((val & (1 << idx)) && !(opp->pint & (1 << idx))) {
}
}
opp->pint = val;
- break;
+ break;
#if MAX_IPI > 0
case 0xA0: /* IPI_IPVP */
case 0xB0:
break;
case 0xF0: /* TIFR */
opp->tifr = val;
- break;
+ break;
default:
break;
}
openpic_t *opp = opaque;
uint32_t retval;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
break;
case 0x20: /* GLBC */
retval = opp->glbc;
- break;
+ break;
case 0x80: /* VENI */
retval = opp->veni;
- break;
+ break;
case 0x90: /* PINT */
retval = 0x00000000;
- break;
+ break;
#if MAX_IPI > 0
case 0xA0: /* IPI_IPVP */
case 0xB0:
idx = (addr - 0xA0) >> 4;
retval = read_IRQreg(opp, opp->irq_ipi0 + idx, IRQ_IPVP);
}
- break;
+ break;
#endif
case 0xE0: /* SPVE */
retval = opp->spve;
break;
case 0xF0: /* TIFR */
retval = opp->tifr;
- break;
+ break;
default:
break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
-#if defined TARGET_WORDS_BIGENDIAN
- retval = openpic_swap32(opp, retval);
-#endif
return retval;
}
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
-#if defined TARGET_WORDS_BIGENDIAN
- val = openpic_swap32(opp, val);
-#endif
addr -= 0x1100;
addr &= 0xFFFF;
idx = (addr & 0xFFF0) >> 6;
case 0x00: /* TICC */
break;
case 0x10: /* TIBC */
- if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
- (val & 0x80000000) == 0 &&
+ if ((opp->timers[idx].ticc & 0x80000000) != 0 &&
+ (val & 0x80000000) == 0 &&
(opp->timers[idx].tibc & 0x80000000) != 0)
- opp->timers[idx].ticc &= ~0x80000000;
- opp->timers[idx].tibc = val;
- break;
+ opp->timers[idx].ticc &= ~0x80000000;
+ opp->timers[idx].tibc = val;
+ break;
case 0x20: /* TIVP */
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP, val);
- break;
+ break;
case 0x30: /* TIDE */
write_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE, val);
- break;
+ break;
}
}
addr = addr & 0x30;
switch (addr) {
case 0x00: /* TICC */
- retval = opp->timers[idx].ticc;
+ retval = opp->timers[idx].ticc;
break;
case 0x10: /* TIBC */
- retval = opp->timers[idx].tibc;
- break;
+ retval = opp->timers[idx].tibc;
+ break;
case 0x20: /* TIPV */
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IPVP);
- break;
+ break;
case 0x30: /* TIDE */
retval = read_IRQreg(opp, opp->irq_tim0 + idx, IRQ_IDE);
- break;
+ break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
-#if defined TARGET_WORDS_BIGENDIAN
- retval = openpic_swap32(opp, retval);
-#endif
return retval;
}
DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
-#if defined TARGET_WORDS_BIGENDIAN
- val = openpic_swap32(opp, val);
-#endif
addr = addr & 0xFFF0;
idx = addr >> 5;
if (addr & 0x10) {
retval = read_IRQreg(opp, idx, IRQ_IPVP);
}
DPRINTF("%s: => %08x\n", __func__, retval);
-#if defined TARGET_WORDS_BIGENDIAN
- retval = openpic_swap32(opp, retval);
-#endif
return retval;
}
IRQ_dst_t *dst;
int idx, s_IRQ, n_IRQ;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
-#if defined TARGET_WORDS_BIGENDIAN
- val = openpic_swap32(opp, val);
-#endif
addr &= 0x1FFF0;
idx = addr / 0x1000;
dst = &opp->dst[idx];
break;
#endif
case 0x80: /* PCTP */
- dst->pctp = val & 0x0000000F;
- break;
+ dst->pctp = val & 0x0000000F;
+ break;
case 0x90: /* WHOAMI */
- /* Read-only register */
- break;
+ /* Read-only register */
+ break;
case 0xA0: /* PIAC */
- /* Read-only register */
- break;
+ /* Read-only register */
+ break;
case 0xB0: /* PEOI */
DPRINTF("PEOI\n");
- s_IRQ = IRQ_get_next(opp, &dst->servicing);
- IRQ_resetbit(&dst->servicing, s_IRQ);
- dst->servicing.next = -1;
- /* Set up next servicing IRQ */
- s_IRQ = IRQ_get_next(opp, &dst->servicing);
+ s_IRQ = IRQ_get_next(opp, &dst->servicing);
+ IRQ_resetbit(&dst->servicing, s_IRQ);
+ dst->servicing.next = -1;
+ /* Set up next servicing IRQ */
+ s_IRQ = IRQ_get_next(opp, &dst->servicing);
/* Check queued interrupts. */
n_IRQ = IRQ_get_next(opp, &dst->raised);
src = &opp->src[n_IRQ];
idx, n_IRQ);
opp->irq_raise(opp, idx, src);
}
- break;
+ break;
default:
break;
}
uint32_t retval;
int idx, n_IRQ;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
addr &= 0xFF0;
switch (addr) {
case 0x80: /* PCTP */
- retval = dst->pctp;
- break;
+ retval = dst->pctp;
+ break;
case 0x90: /* WHOAMI */
- retval = idx;
- break;
+ retval = idx;
+ break;
case 0xA0: /* PIAC */
DPRINTF("Lower OpenPIC INT output\n");
qemu_irq_lower(dst->irqs[OPENPIC_OUTPUT_INT]);
- n_IRQ = IRQ_get_next(opp, &dst->raised);
+ n_IRQ = IRQ_get_next(opp, &dst->raised);
DPRINTF("PIAC: irq=%d\n", n_IRQ);
- if (n_IRQ == -1) {
- /* No more interrupt pending */
+ if (n_IRQ == -1) {
+ /* No more interrupt pending */
retval = IPVP_VECTOR(opp->spve);
- } else {
- src = &opp->src[n_IRQ];
- if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
- !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
- /* - Spurious level-sensitive IRQ
- * - Priorities has been changed
- * and the pending IRQ isn't allowed anymore
- */
- reset_bit(&src->ipvp, IPVP_ACTIVITY);
- retval = IPVP_VECTOR(opp->spve);
- } else {
- /* IRQ enter servicing state */
- IRQ_setbit(&dst->servicing, n_IRQ);
- retval = IPVP_VECTOR(src->ipvp);
- }
- IRQ_resetbit(&dst->raised, n_IRQ);
- dst->raised.next = -1;
- if (!test_bit(&src->ipvp, IPVP_SENSE)) {
+ } else {
+ src = &opp->src[n_IRQ];
+ if (!test_bit(&src->ipvp, IPVP_ACTIVITY) ||
+ !(IPVP_PRIORITY(src->ipvp) > dst->pctp)) {
+ /* - Spurious level-sensitive IRQ
+ * - Priorities has been changed
+ * and the pending IRQ isn't allowed anymore
+ */
+ reset_bit(&src->ipvp, IPVP_ACTIVITY);
+ retval = IPVP_VECTOR(opp->spve);
+ } else {
+ /* IRQ enter servicing state */
+ IRQ_setbit(&dst->servicing, n_IRQ);
+ retval = IPVP_VECTOR(src->ipvp);
+ }
+ IRQ_resetbit(&dst->raised, n_IRQ);
+ dst->raised.next = -1;
+ if (!test_bit(&src->ipvp, IPVP_SENSE)) {
/* edge-sensitive IRQ */
- reset_bit(&src->ipvp, IPVP_ACTIVITY);
+ reset_bit(&src->ipvp, IPVP_ACTIVITY);
src->pending = 0;
}
- }
- break;
+ }
+ break;
case 0xB0: /* PEOI */
- retval = 0;
- break;
+ retval = 0;
+ break;
#if MAX_IPI > 0
case 0x40: /* IDE */
case 0x50:
break;
}
DPRINTF("%s: => %08x\n", __func__, retval);
-#if defined TARGET_WORDS_BIGENDIAN
- retval = openpic_swap32(opp, retval);
-#endif
return retval;
}
return retval;
}
-static CPUWriteMemoryFunc *openpic_write[] = {
+static CPUWriteMemoryFunc * const openpic_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_writel,
};
-static CPUReadMemoryFunc *openpic_read[] = {
+static CPUReadMemoryFunc * const openpic_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_readl,
};
static void openpic_map(PCIDevice *pci_dev, int region_num,
- uint32_t addr, uint32_t size, int type)
+ pcibus_t addr, pcibus_t size, int type)
{
openpic_t *opp;
addr + 0x20000, addr + 0x20000 + 0x1000 * MAX_CPU);
cpu_register_physical_memory(addr, 0x40000, opp->mem_index);
#if 0 // Don't implement ISU for now
- opp_io_memory = cpu_register_io_memory(0, openpic_src_read,
- openpic_src_write);
+ opp_io_memory = cpu_register_io_memory(openpic_src_read,
+ openpic_src_write, NULL
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(isu_base, 0x20 * (EXT_IRQ + 2),
opp_io_memory);
#endif
if (bus) {
opp = (openpic_t *)pci_register_device(bus, "OpenPIC", sizeof(openpic_t),
-1, NULL, NULL);
- if (opp == NULL)
- return NULL;
pci_conf = opp->pci_dev.config;
pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_IBM);
pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_IBM_OPENPIC2);
pci_config_set_class(pci_conf, PCI_CLASS_SYSTEM_OTHER); // FIXME?
- pci_conf[0x0e] = 0x00; // header_type
pci_conf[0x3d] = 0x00; // no interrupt pin
/* Register I/O spaces */
- pci_register_io_region((PCIDevice *)opp, 0, 0x40000,
- PCI_ADDRESS_SPACE_MEM, &openpic_map);
+ pci_register_bar(&opp->pci_dev, 0, 0x40000,
+ PCI_BASE_ADDRESS_SPACE_MEMORY, &openpic_map);
} else {
opp = qemu_mallocz(sizeof(openpic_t));
}
- opp->mem_index = cpu_register_io_memory(0, openpic_read,
- openpic_write, opp);
+ opp->mem_index = cpu_register_io_memory(openpic_read, openpic_write, opp,
+ DEVICE_LITTLE_ENDIAN);
// isu_base &= 0xFFFC0000;
opp->nb_cpus = nb_cpus;
for (i = 0; i < nb_cpus; i++)
opp->dst[i].irqs = irqs[i];
opp->irq_out = irq_out;
- opp->need_swap = 1;
- register_savevm("openpic", 0, 2, openpic_save, openpic_load, opp);
+ register_savevm(&opp->pci_dev.qdev, "openpic", 0, 2,
+ openpic_save, openpic_load, opp);
qemu_register_reset(openpic_reset, opp);
opp->irq_raise = openpic_irq_raise;
opp->reset = openpic_reset;
- opp->reset(opp);
if (pmem_index)
*pmem_index = opp->mem_index;
static void mpic_irq_raise(openpic_t *mpp, int n_CPU, IRQ_src_t *src)
{
int n_ci = IDR_CI0 - n_CPU;
- DPRINTF("%s: cpu:%d irq:%d (testbit idr:%x ci:%d)\n", __func__,
- n_CPU, n_IRQ, mpp->src[n_IRQ].ide, n_ci);
+
if(test_bit(&src->ide, n_ci)) {
qemu_irq_raise(mpp->dst[n_CPU].irqs[OPENPIC_OUTPUT_CINT]);
}
openpic_t *mpp = opaque;
int idx, cpu;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
addr &= 0xFFFF;
uint32_t retval;
int idx, cpu;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
openpic_t *mpp = opaque;
int idx = MPIC_EXT_IRQ;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_EXT_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
uint32_t retval;
int idx = MPIC_EXT_IRQ;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
- addr -= MPIC_EXT_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_EXT_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_EXT_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
openpic_t *mpp = opaque;
int idx = MPIC_INT_IRQ;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_INT_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
uint32_t retval;
int idx = MPIC_INT_IRQ;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
- addr -= MPIC_INT_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_INT_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_INT_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
openpic_t *mpp = opaque;
int idx = MPIC_MSG_IRQ;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_MSG_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
uint32_t retval;
int idx = MPIC_MSG_IRQ;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
- addr -= MPIC_MSG_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_MSG_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_MSG_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
openpic_t *mpp = opaque;
int idx = MPIC_MSI_IRQ;
- DPRINTF("%s: addr %08x <= %08x\n", __func__, addr, val);
+ DPRINTF("%s: addr " TARGET_FMT_plx " <= %08x\n", __func__, addr, val);
if (addr & 0xF)
return;
- addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_MSI_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
uint32_t retval;
int idx = MPIC_MSI_IRQ;
- DPRINTF("%s: addr %08x\n", __func__, addr);
+ DPRINTF("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
retval = 0xFFFFFFFF;
if (addr & 0xF)
return retval;
- addr -= MPIC_MSI_REG_START & (TARGET_PAGE_SIZE - 1);
+ addr -= MPIC_MSI_REG_START & (OPENPIC_PAGE_SIZE - 1);
if (addr < MPIC_MSI_REG_SIZE) {
idx += (addr & 0xFFF0) >> 5;
if (addr & 0x10) {
return retval;
}
-static CPUWriteMemoryFunc *mpic_glb_write[] = {
+static CPUWriteMemoryFunc * const mpic_glb_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_gbl_write,
};
-static CPUReadMemoryFunc *mpic_glb_read[] = {
+static CPUReadMemoryFunc * const mpic_glb_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_gbl_read,
};
-static CPUWriteMemoryFunc *mpic_tmr_write[] = {
+static CPUWriteMemoryFunc * const mpic_tmr_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_timer_write,
};
-static CPUReadMemoryFunc *mpic_tmr_read[] = {
+static CPUReadMemoryFunc * const mpic_tmr_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_timer_read,
};
-static CPUWriteMemoryFunc *mpic_cpu_write[] = {
+static CPUWriteMemoryFunc * const mpic_cpu_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&openpic_cpu_write,
};
-static CPUReadMemoryFunc *mpic_cpu_read[] = {
+static CPUReadMemoryFunc * const mpic_cpu_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&openpic_cpu_read,
};
-static CPUWriteMemoryFunc *mpic_ext_write[] = {
+static CPUWriteMemoryFunc * const mpic_ext_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_ext_write,
};
-static CPUReadMemoryFunc *mpic_ext_read[] = {
+static CPUReadMemoryFunc * const mpic_ext_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_ext_read,
};
-static CPUWriteMemoryFunc *mpic_int_write[] = {
+static CPUWriteMemoryFunc * const mpic_int_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_int_write,
};
-static CPUReadMemoryFunc *mpic_int_read[] = {
+static CPUReadMemoryFunc * const mpic_int_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_int_read,
};
-static CPUWriteMemoryFunc *mpic_msg_write[] = {
+static CPUWriteMemoryFunc * const mpic_msg_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_msg_write,
};
-static CPUReadMemoryFunc *mpic_msg_read[] = {
+static CPUReadMemoryFunc * const mpic_msg_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_msg_read,
};
-static CPUWriteMemoryFunc *mpic_msi_write[] = {
+static CPUWriteMemoryFunc * const mpic_msi_write[] = {
&openpic_buggy_write,
&openpic_buggy_write,
&mpic_src_msi_write,
};
-static CPUReadMemoryFunc *mpic_msi_read[] = {
+static CPUReadMemoryFunc * const mpic_msi_read[] = {
&openpic_buggy_read,
&openpic_buggy_read,
&mpic_src_msi_read,
openpic_t *mpp;
int i;
struct {
- CPUReadMemoryFunc **read;
- CPUWriteMemoryFunc **write;
+ CPUReadMemoryFunc * const *read;
+ CPUWriteMemoryFunc * const *write;
target_phys_addr_t start_addr;
ram_addr_t size;
} const list[] = {
for (i = 0; i < sizeof(list)/sizeof(list[0]); i++) {
int mem_index;
- mem_index = cpu_register_io_memory(0, list[i].read, list[i].write, mpp);
+ mem_index = cpu_register_io_memory(list[i].read, list[i].write, mpp,
+ DEVICE_BIG_ENDIAN);
if (mem_index < 0) {
goto free;
}
for (i = 0; i < nb_cpus; i++)
mpp->dst[i].irqs = irqs[i];
mpp->irq_out = irq_out;
- mpp->need_swap = 0; /* MPIC has the same endian as target */
mpp->irq_raise = mpic_irq_raise;
mpp->reset = mpic_reset;
- register_savevm("mpic", 0, 2, openpic_save, openpic_load, mpp);
+ register_savevm(NULL, "mpic", 0, 2, openpic_save, openpic_load, mpp);
qemu_register_reset(mpic_reset, mpp);
- mpp->reset(mpp);
return qemu_allocate_irqs(openpic_set_irq, mpp, mpp->max_irq);
projects / qemu.git / blobdiff