#include "sysbus.h"
#include "sysemu.h"
#include "blockdev.h"
+#include "ui/qemu-spice.h"
/* output Bochs bios info messages */
//#define DEBUG_BIOS
uint64_t address;
uint64_t length;
uint32_t type;
-};
+} __attribute((__packed__, __aligned__(4)));
struct e820_table {
uint32_t count;
struct e820_entry entry[E820_NR_ENTRIES];
-};
+} __attribute((__packed__, __aligned__(4)));
static struct e820_table e820_table;
qemu_register_reset(pc_cmos_init_late, &arg);
}
+/* port 92 stuff: could be split off */
+typedef struct Port92State {
+ ISADevice dev;
+ uint8_t outport;
+ qemu_irq *a20_out;
+} Port92State;
+
+static void port92_write(void *opaque, uint32_t addr, uint32_t val)
+{
+ Port92State *s = opaque;
+
+ DPRINTF("port92: write 0x%02x\n", val);
+ s->outport = val;
+ qemu_set_irq(*s->a20_out, (val >> 1) & 1);
+ if (val & 1) {
+ qemu_system_reset_request();
+ }
+}
+
+static uint32_t port92_read(void *opaque, uint32_t addr)
+{
+ Port92State *s = opaque;
+ uint32_t ret;
+
+ ret = s->outport;
+ DPRINTF("port92: read 0x%02x\n", ret);
+ return ret;
+}
+
+static void port92_init(ISADevice *dev, qemu_irq *a20_out)
+{
+ Port92State *s = DO_UPCAST(Port92State, dev, dev);
+
+ s->a20_out = a20_out;
+}
+
+static const VMStateDescription vmstate_port92_isa = {
+ .name = "port92",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT8(outport, Port92State),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static void port92_reset(DeviceState *d)
+{
+ Port92State *s = container_of(d, Port92State, dev.qdev);
+
+ s->outport &= ~1;
+}
+
+static int port92_initfn(ISADevice *dev)
+{
+ Port92State *s = DO_UPCAST(Port92State, dev, dev);
+
+ register_ioport_read(0x92, 1, 1, port92_read, s);
+ register_ioport_write(0x92, 1, 1, port92_write, s);
+ isa_init_ioport(dev, 0x92);
+ s->outport = 0;
+ return 0;
+}
+
+static ISADeviceInfo port92_info = {
+ .qdev.name = "port92",
+ .qdev.size = sizeof(Port92State),
+ .qdev.vmsd = &vmstate_port92_isa,
+ .qdev.no_user = 1,
+ .qdev.reset = port92_reset,
+ .init = port92_initfn,
+};
+
+static void port92_register(void)
+{
+ isa_qdev_register(&port92_info);
+}
+device_init(port92_register)
+
static void handle_a20_line_change(void *opaque, int irq, int level)
{
CPUState *cpu = opaque;
/* XXX: send to all CPUs ? */
+ /* XXX: add logic to handle multiple A20 line sources */
cpu_x86_set_a20(cpu, level);
}
/* Bochs BIOS messages */
case 0x400:
case 0x401:
- fprintf(stderr, "BIOS panic at rombios.c, line %d\n", val);
- exit(1);
+ /* used to be panic, now unused */
+ break;
case 0x402:
case 0x403:
#ifdef DEBUG_BIOS
int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
{
- int index = e820_table.count;
+ int index = le32_to_cpu(e820_table.count);
struct e820_entry *entry;
if (index >= E820_NR_ENTRIES)
return -EBUSY;
- entry = &e820_table.entry[index];
+ entry = &e820_table.entry[index++];
- entry->address = address;
- entry->length = length;
- entry->type = type;
+ entry->address = cpu_to_le64(address);
+ entry->length = cpu_to_le64(length);
+ entry->type = cpu_to_le32(type);
- e820_table.count++;
- return e820_table.count;
+ e820_table.count = cpu_to_le32(index);
+ return index;
}
static void *bochs_bios_init(void)
fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
- option_rom[nb_option_roms] = "linuxboot.bin";
+ option_rom[nb_option_roms].name = "linuxboot.bin";
+ option_rom[nb_option_roms].bootindex = 0;
nb_option_roms++;
}
static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
-void pc_audio_init (PCIBus *pci_bus, qemu_irq *pic)
-{
- struct soundhw *c;
-
- for (c = soundhw; c->name; ++c) {
- if (c->enabled) {
- if (c->isa) {
- c->init.init_isa(pic);
- } else {
- if (pci_bus) {
- c->init.init_pci(pci_bus);
- }
- }
- }
- }
-}
-
void pc_init_ne2k_isa(NICInfo *nd)
{
static int nb_ne2k = 0;
goto bios_error;
}
bios_offset = qemu_ram_alloc(NULL, "pc.bios", bios_size);
- ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size));
+ ret = rom_add_file_fixed(bios_name, (uint32_t)(-bios_size), -1);
if (ret != 0) {
bios_error:
fprintf(stderr, "qemu: could not load PC BIOS '%s'\n", bios_name);
}
for (i = 0; i < nb_option_roms; i++) {
- rom_add_option(option_rom[i]);
+ rom_add_option(option_rom[i].name, option_rom[i].bootindex);
}
}
pci_vmsvga_init(pci_bus);
else
fprintf(stderr, "%s: vmware_vga: no PCI bus\n", __FUNCTION__);
+#ifdef CONFIG_SPICE
+ } else if (qxl_enabled) {
+ if (pci_bus)
+ pci_create_simple(pci_bus, -1, "qxl-vga");
+ else
+ fprintf(stderr, "%s: qxl: no PCI bus\n", __FUNCTION__);
+#endif
} else if (std_vga_enabled) {
if (pci_bus) {
pci_vga_init(pci_bus);
PITState *pit;
qemu_irq rtc_irq = NULL;
qemu_irq *a20_line;
- ISADevice *i8042;
+ ISADevice *i8042, *port92;
qemu_irq *cpu_exit_irq;
register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
qemu_register_boot_set(pc_boot_set, *rtc_state);
- pit = pit_init(0x40, isa_reserve_irq(0));
+ pit = pit_init(0x40, isa_get_irq(0));
pcspk_init(pit);
for(i = 0; i < MAX_SERIAL_PORTS; i++) {
}
}
- a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 1);
+ a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
i8042 = isa_create_simple("i8042");
- i8042_setup_a20_line(i8042, a20_line);
+ i8042_setup_a20_line(i8042, &a20_line[0]);
vmmouse_init(i8042);
+ port92 = isa_create_simple("port92");
+ port92_init(port92, &a20_line[1]);
cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
DMA_init(0, cpu_exit_irq);
projects / qemu.git / blobdiff