ide: Split error status from status register

[qemu.git] / hw / pci_host.c

diff --git a/hw/pci_host.c b/hw/pci_host.c
index b15d5faef73a0e7e613483894869594ee05f6574..728e2d4ce50ca46f4a3b4cd06194ab16ea769aa9 100644 (file)
--- a/hw/pci_host.c
+++ b/hw/pci_host.c
@@ -15,8 +15,7 @@
  * GNU General Public License for more details.
 
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 
 #include "pci.h"
@@ -45,7 +44,7 @@ static inline PCIDevice *pci_dev_find_by_addr(PCIBus *bus, uint32_t addr)
     uint8_t bus_num = addr >> 16;
     uint8_t devfn = addr >> 8;
 
-    return pci_find_device(bus, bus_num, PCI_SLOT(devfn), PCI_FUNC(devfn));
+    return pci_find_device(bus, bus_num, devfn);
 }
 
 void pci_data_write(PCIBus *s, uint32_t addr, uint32_t val, int len)
@@ -86,40 +85,14 @@ static void pci_host_config_write(ReadWriteHandler *handler,
 
     PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
                 __func__, addr, len, val);
-#ifdef TARGET_WORDS_BIGENDIAN
-    val = qemu_bswap_len(val, len);
-#endif
     s->config_reg = val;
 }
 
 static uint32_t pci_host_config_read(ReadWriteHandler *handler,
-                                            pcibus_t addr, int len)
+                                     pcibus_t addr, int len)
 {
     PCIHostState *s = container_of(handler, PCIHostState, conf_handler);
     uint32_t val = s->config_reg;
-#ifdef TARGET_WORDS_BIGENDIAN
-    val = qemu_bswap_len(val, len);
-#endif
-    PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
-                __func__, addr, len, val);
-    return val;
-}
-
-static void pci_host_config_write_noswap(ReadWriteHandler *handler,
-                                         pcibus_t addr, uint32_t val, int len)
-{
-    PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-
-    PCI_DPRINTF("%s addr %" FMT_PCIBUS " %d val %"PRIx32"\n",
-                __func__, addr, len, val);
-    s->config_reg = val;
-}
-
-static uint32_t pci_host_config_read_noswap(ReadWriteHandler *handler,
-                                            pcibus_t addr, int len)
-{
-    PCIHostState *s = container_of(handler, PCIHostState, conf_noswap_handler);
-    uint32_t val = s->config_reg;
 
     PCI_DPRINTF("%s addr %" FMT_PCIBUS " len %d val %"PRIx32"\n",
                 __func__, addr, len, val);
@@ -130,9 +103,6 @@ static void pci_host_data_write(ReadWriteHandler *handler,
                                 pcibus_t addr, uint32_t val, int len)
 {
     PCIHostState *s = container_of(handler, PCIHostState, data_handler);
-#ifdef TARGET_WORDS_BIGENDIAN
-    val = qemu_bswap_len(val, len);
-#endif
     PCI_DPRINTF("write addr %" FMT_PCIBUS " len %d val %x\n",
                 addr, len, val);
     if (s->config_reg & (1u << 31))
@@ -149,9 +119,6 @@ static uint32_t pci_host_data_read(ReadWriteHandler *handler,
     val = pci_data_read(s->bus, s->config_reg | (addr & 3), len);
     PCI_DPRINTF("read addr %" FMT_PCIBUS " len %d val %x\n",
                 addr, len, val);
-#ifdef TARGET_WORDS_BIGENDIAN
-    val = qemu_bswap_len(val, len);
-#endif
     return val;
 }
 
@@ -159,34 +126,27 @@ static void pci_host_init(PCIHostState *s)
 {
     s->conf_handler.write = pci_host_config_write;
     s->conf_handler.read = pci_host_config_read;
-    s->conf_noswap_handler.write = pci_host_config_write_noswap;
-    s->conf_noswap_handler.read = pci_host_config_read_noswap;
     s->data_handler.write = pci_host_data_write;
     s->data_handler.read = pci_host_data_read;
 }
 
-int pci_host_conf_register_mmio(PCIHostState *s)
-{
-    pci_host_init(s);
-    return cpu_register_io_memory_simple(&s->conf_handler);
-}
-
-int pci_host_conf_register_mmio_noswap(PCIHostState *s)
+int pci_host_conf_register_mmio(PCIHostState *s, int endian)
 {
     pci_host_init(s);
-    return cpu_register_io_memory_simple(&s->conf_noswap_handler);
+    return cpu_register_io_memory_simple(&s->conf_handler, endian);
 }
 
 void pci_host_conf_register_ioport(pio_addr_t ioport, PCIHostState *s)
 {
     pci_host_init(s);
-    register_ioport_simple(&s->conf_noswap_handler, ioport, 4, 4);
+    register_ioport_simple(&s->conf_handler, ioport, 4, 4);
+    sysbus_init_ioports(&s->busdev, ioport, 4);
 }
 
-int pci_host_data_register_mmio(PCIHostState *s)
+int pci_host_data_register_mmio(PCIHostState *s, int endian)
 {
     pci_host_init(s);
-    return cpu_register_io_memory_simple(&s->data_handler);
+    return cpu_register_io_memory_simple(&s->data_handler, endian);
 }
 
 void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
@@ -195,4 +155,5 @@ void pci_host_data_register_ioport(pio_addr_t ioport, PCIHostState *s)
     register_ioport_simple(&s->data_handler, ioport, 4, 1);
     register_ioport_simple(&s->data_handler, ioport, 4, 2);
     register_ioport_simple(&s->data_handler, ioport, 4, 4);
+    sysbus_init_ioports(&s->busdev, ioport, 4);
 }