* This code is licenced under the GPL.
*/
-#include "hw.h"
+#include "sysbus.h"
#include "qemu-char.h"
-#include "primecell.h"
typedef struct {
+ SysBusDevice busdev;
uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
int read_trigger;
CharDriverState *chr;
qemu_irq irq;
- enum pl011_type type;
+ const unsigned char *id;
} pl011_state;
#define PL011_INT_TX 0x20
#define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10
-static const unsigned char pl011_id[2][8] = {
- { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_ARM */
- { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }, /* PL011_LUMINARY */
-};
+static const unsigned char pl011_id_arm[8] =
+ { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl011_id_luminary[8] =
+ { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
static void pl011_update(pl011_state *s)
{
uint32_t c;
if (offset >= 0xfe0 && offset < 0x1000) {
- return pl011_id[s->type][(offset - 0xfe0) >> 2];
+ return s->id[(offset - 0xfe0) >> 2];
}
switch (offset >> 2) {
case 0: /* UARTDR */
case 18: /* UARTDMACR */
return s->dmacr;
default:
- cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", (int)offset);
+ hw_error("pl011_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 18: /* UARTDMACR */
s->dmacr = value;
if (value & 3)
- cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
+ hw_error("PL011: DMA not implemented\n");
break;
default:
- cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", (int)offset);
+ hw_error("pl011_write: Bad offset %x\n", (int)offset);
}
}
pl011_put_fifo(opaque, 0x400);
}
-static CPUReadMemoryFunc *pl011_readfn[] = {
+static CPUReadMemoryFunc * const pl011_readfn[] = {
pl011_read,
pl011_read,
pl011_read
};
-static CPUWriteMemoryFunc *pl011_writefn[] = {
+static CPUWriteMemoryFunc * const pl011_writefn[] = {
pl011_write,
pl011_write,
pl011_write
};
-static void pl011_save(QEMUFile *f, void *opaque)
-{
- pl011_state *s = (pl011_state *)opaque;
- int i;
-
- qemu_put_be32(f, s->readbuff);
- qemu_put_be32(f, s->flags);
- qemu_put_be32(f, s->lcr);
- qemu_put_be32(f, s->cr);
- qemu_put_be32(f, s->dmacr);
- qemu_put_be32(f, s->int_enabled);
- qemu_put_be32(f, s->int_level);
- for (i = 0; i < 16; i++)
- qemu_put_be32(f, s->read_fifo[i]);
- qemu_put_be32(f, s->ilpr);
- qemu_put_be32(f, s->ibrd);
- qemu_put_be32(f, s->fbrd);
- qemu_put_be32(f, s->ifl);
- qemu_put_be32(f, s->read_pos);
- qemu_put_be32(f, s->read_count);
- qemu_put_be32(f, s->read_trigger);
-}
-
-static int pl011_load(QEMUFile *f, void *opaque, int version_id)
-{
- pl011_state *s = (pl011_state *)opaque;
- int i;
-
- if (version_id != 1)
- return -EINVAL;
-
- s->readbuff = qemu_get_be32(f);
- s->flags = qemu_get_be32(f);
- s->lcr = qemu_get_be32(f);
- s->cr = qemu_get_be32(f);
- s->dmacr = qemu_get_be32(f);
- s->int_enabled = qemu_get_be32(f);
- s->int_level = qemu_get_be32(f);
- for (i = 0; i < 16; i++)
- s->read_fifo[i] = qemu_get_be32(f);
- s->ilpr = qemu_get_be32(f);
- s->ibrd = qemu_get_be32(f);
- s->fbrd = qemu_get_be32(f);
- s->ifl = qemu_get_be32(f);
- s->read_pos = qemu_get_be32(f);
- s->read_count = qemu_get_be32(f);
- s->read_trigger = qemu_get_be32(f);
-
- return 0;
-}
+static const VMStateDescription vmstate_pl011 = {
+ .name = "pl011",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(readbuff, pl011_state),
+ VMSTATE_UINT32(flags, pl011_state),
+ VMSTATE_UINT32(lcr, pl011_state),
+ VMSTATE_UINT32(cr, pl011_state),
+ VMSTATE_UINT32(dmacr, pl011_state),
+ VMSTATE_UINT32(int_enabled, pl011_state),
+ VMSTATE_UINT32(int_level, pl011_state),
+ VMSTATE_UINT32_ARRAY(read_fifo, pl011_state, 16),
+ VMSTATE_UINT32(ilpr, pl011_state),
+ VMSTATE_UINT32(ibrd, pl011_state),
+ VMSTATE_UINT32(fbrd, pl011_state),
+ VMSTATE_UINT32(ifl, pl011_state),
+ VMSTATE_INT32(read_pos, pl011_state),
+ VMSTATE_INT32(read_count, pl011_state),
+ VMSTATE_INT32(read_trigger, pl011_state),
+ VMSTATE_END_OF_LIST()
+ }
+};
-void pl011_init(uint32_t base, qemu_irq irq,
- CharDriverState *chr, enum pl011_type type)
+static int pl011_init(SysBusDevice *dev, const unsigned char *id)
{
int iomemtype;
- pl011_state *s;
+ pl011_state *s = FROM_SYSBUS(pl011_state, dev);
+
+ iomemtype = cpu_register_io_memory(pl011_readfn,
+ pl011_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, 0x1000,iomemtype);
+ sysbus_init_irq(dev, &s->irq);
+ s->id = id;
+ s->chr = qdev_init_chardev(&dev->qdev);
- s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
- iomemtype = cpu_register_io_memory(0, pl011_readfn,
- pl011_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->irq = irq;
- s->type = type;
- s->chr = chr;
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0x90;
- if (chr){
- qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
+ if (s->chr) {
+ qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
- register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);
+ vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
+ return 0;
+}
+
+static int pl011_init_arm(SysBusDevice *dev)
+{
+ return pl011_init(dev, pl011_id_arm);
+}
+
+static int pl011_init_luminary(SysBusDevice *dev)
+{
+ return pl011_init(dev, pl011_id_luminary);
+}
+
+static void pl011_register_devices(void)
+{
+ sysbus_register_dev("pl011", sizeof(pl011_state),
+ pl011_init_arm);
+ sysbus_register_dev("pl011_luminary", sizeof(pl011_state),
+ pl011_init_luminary);
}
+device_init(pl011_register_devices)
projects / qemu.git / blobdiff