* This code is licenced under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "qemu-char.h"
+#include "primecell.h"
typedef struct {
- uint32_t base;
uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
pl011_state *s = (pl011_state *)opaque;
uint32_t c;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl011_id[s->type][(offset - 0xfe0) >> 2];
}
if (s->read_count == s->read_trigger - 1)
s->int_level &= ~ PL011_INT_RX;
pl011_update(s);
+ qemu_chr_accept_input(s->chr);
return c;
case 1: /* UARTCR */
return 0;
pl011_state *s = (pl011_state *)opaque;
unsigned char ch;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* UARTDR */
/* ??? Check if transmitter is enabled. */
return s->read_count < 1;
}
-static void pl011_receive(void *opaque, const uint8_t *buf, int size)
+static void pl011_put_fifo(void *opaque, uint32_t value)
{
pl011_state *s = (pl011_state *)opaque;
int slot;
slot = s->read_pos + s->read_count;
if (slot >= 16)
slot -= 16;
- s->read_fifo[slot] = *buf;
+ s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
if (s->cr & 0x10 || s->read_count == 16) {
}
}
+static void pl011_receive(void *opaque, const uint8_t *buf, int size)
+{
+ pl011_put_fifo(opaque, *buf);
+}
+
static void pl011_event(void *opaque, int event)
{
- /* ??? Should probably implement break. */
+ if (event == CHR_EVENT_BREAK)
+ pl011_put_fifo(opaque, 0x400);
}
static CPUReadMemoryFunc *pl011_readfn[] = {
pl011_write
};
+static void pl011_save(QEMUFile *f, void *opaque)
+{
+ pl011_state *s = (pl011_state *)opaque;
+ int i;
+
+ qemu_put_be32(f, s->readbuff);
+ qemu_put_be32(f, s->flags);
+ qemu_put_be32(f, s->lcr);
+ qemu_put_be32(f, s->cr);
+ qemu_put_be32(f, s->dmacr);
+ qemu_put_be32(f, s->int_enabled);
+ qemu_put_be32(f, s->int_level);
+ for (i = 0; i < 16; i++)
+ qemu_put_be32(f, s->read_fifo[i]);
+ qemu_put_be32(f, s->ilpr);
+ qemu_put_be32(f, s->ibrd);
+ qemu_put_be32(f, s->fbrd);
+ qemu_put_be32(f, s->ifl);
+ qemu_put_be32(f, s->read_pos);
+ qemu_put_be32(f, s->read_count);
+ qemu_put_be32(f, s->read_trigger);
+}
+
+static int pl011_load(QEMUFile *f, void *opaque, int version_id)
+{
+ pl011_state *s = (pl011_state *)opaque;
+ int i;
+
+ if (version_id != 1)
+ return -EINVAL;
+
+ s->readbuff = qemu_get_be32(f);
+ s->flags = qemu_get_be32(f);
+ s->lcr = qemu_get_be32(f);
+ s->cr = qemu_get_be32(f);
+ s->dmacr = qemu_get_be32(f);
+ s->int_enabled = qemu_get_be32(f);
+ s->int_level = qemu_get_be32(f);
+ for (i = 0; i < 16; i++)
+ s->read_fifo[i] = qemu_get_be32(f);
+ s->ilpr = qemu_get_be32(f);
+ s->ibrd = qemu_get_be32(f);
+ s->fbrd = qemu_get_be32(f);
+ s->ifl = qemu_get_be32(f);
+ s->read_pos = qemu_get_be32(f);
+ s->read_count = qemu_get_be32(f);
+ s->read_trigger = qemu_get_be32(f);
+
+ return 0;
+}
+
void pl011_init(uint32_t base, qemu_irq irq,
CharDriverState *chr, enum pl011_type type)
{
iomemtype = cpu_register_io_memory(0, pl011_readfn,
pl011_writefn, s);
cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
s->irq = irq;
s->type = type;
s->chr = chr;
qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
- /* ??? Save/restore. */
+ register_savevm("pl011_uart", -1, 1, pl011_save, pl011_load, s);
}
-