-/*
+/*
* Arm PrimeCell PL011 UART
*
* Copyright (c) 2006 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
-#include "vl.h"
+#include "sysbus.h"
+#include "qemu-char.h"
typedef struct {
- uint32_t base;
+ SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t readbuff;
uint32_t flags;
uint32_t lcr;
int read_trigger;
CharDriverState *chr;
qemu_irq irq;
+ const unsigned char *id;
} pl011_state;
#define PL011_INT_TX 0x20
#define PL011_FLAG_TXFF 0x20
#define PL011_FLAG_RXFE 0x10
-static const unsigned char pl011_id[] =
-{ 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl011_id_arm[8] =
+ { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 };
+static const unsigned char pl011_id_luminary[8] =
+ { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 };
static void pl011_update(pl011_state *s)
{
uint32_t flags;
-
+
flags = s->int_level & s->int_enabled;
qemu_set_irq(s->irq, flags != 0);
}
-static uint32_t pl011_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pl011_read(void *opaque, target_phys_addr_t offset,
+ unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
uint32_t c;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
- return pl011_id[(offset - 0xfe0) >> 2];
+ return s->id[(offset - 0xfe0) >> 2];
}
switch (offset >> 2) {
case 0: /* UARTDR */
if (s->read_count == s->read_trigger - 1)
s->int_level &= ~ PL011_INT_RX;
pl011_update(s);
+ qemu_chr_accept_input(s->chr);
return c;
case 1: /* UARTCR */
return 0;
case 18: /* UARTDMACR */
return s->dmacr;
default:
- cpu_abort (cpu_single_env, "pl011_read: Bad offset %x\n", offset);
+ hw_error("pl011_read: Bad offset %x\n", (int)offset);
return 0;
}
}
}
static void pl011_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+ uint64_t value, unsigned size)
{
pl011_state *s = (pl011_state *)opaque;
unsigned char ch;
- offset -= s->base;
switch (offset >> 2) {
case 0: /* UARTDR */
/* ??? Check if transmitter is enabled. */
ch = value;
if (s->chr)
- qemu_chr_write(s->chr, &ch, 1);
+ qemu_chr_fe_write(s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
pl011_update(s);
break;
case 1: /* UARTCR */
s->cr = value;
break;
+ case 6: /* UARTFR */
+ /* Writes to Flag register are ignored. */
+ break;
case 8: /* UARTUARTILPR */
s->ilpr = value;
break;
case 18: /* UARTDMACR */
s->dmacr = value;
if (value & 3)
- cpu_abort(cpu_single_env, "PL011: DMA not implemented\n");
+ hw_error("PL011: DMA not implemented\n");
break;
default:
- cpu_abort (cpu_single_env, "pl011_write: Bad offset %x\n", offset);
+ hw_error("pl011_write: Bad offset %x\n", (int)offset);
}
}
return s->read_count < 1;
}
-static void pl011_receive(void *opaque, const uint8_t *buf, int size)
+static void pl011_put_fifo(void *opaque, uint32_t value)
{
pl011_state *s = (pl011_state *)opaque;
int slot;
slot = s->read_pos + s->read_count;
if (slot >= 16)
slot -= 16;
- s->read_fifo[slot] = *buf;
+ s->read_fifo[slot] = value;
s->read_count++;
s->flags &= ~PL011_FLAG_RXFE;
if (s->cr & 0x10 || s->read_count == 16) {
}
}
+static void pl011_receive(void *opaque, const uint8_t *buf, int size)
+{
+ pl011_put_fifo(opaque, *buf);
+}
+
static void pl011_event(void *opaque, int event)
{
- /* ??? Should probably implement break. */
+ if (event == CHR_EVENT_BREAK)
+ pl011_put_fifo(opaque, 0x400);
}
-static CPUReadMemoryFunc *pl011_readfn[] = {
- pl011_read,
- pl011_read,
- pl011_read
+static const MemoryRegionOps pl011_ops = {
+ .read = pl011_read,
+ .write = pl011_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc *pl011_writefn[] = {
- pl011_write,
- pl011_write,
- pl011_write
+static const VMStateDescription vmstate_pl011 = {
+ .name = "pl011",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(readbuff, pl011_state),
+ VMSTATE_UINT32(flags, pl011_state),
+ VMSTATE_UINT32(lcr, pl011_state),
+ VMSTATE_UINT32(cr, pl011_state),
+ VMSTATE_UINT32(dmacr, pl011_state),
+ VMSTATE_UINT32(int_enabled, pl011_state),
+ VMSTATE_UINT32(int_level, pl011_state),
+ VMSTATE_UINT32_ARRAY(read_fifo, pl011_state, 16),
+ VMSTATE_UINT32(ilpr, pl011_state),
+ VMSTATE_UINT32(ibrd, pl011_state),
+ VMSTATE_UINT32(fbrd, pl011_state),
+ VMSTATE_UINT32(ifl, pl011_state),
+ VMSTATE_INT32(read_pos, pl011_state),
+ VMSTATE_INT32(read_count, pl011_state),
+ VMSTATE_INT32(read_trigger, pl011_state),
+ VMSTATE_END_OF_LIST()
+ }
};
-void pl011_init(uint32_t base, qemu_irq irq,
- CharDriverState *chr)
+static int pl011_init(SysBusDevice *dev, const unsigned char *id)
{
- int iomemtype;
- pl011_state *s;
-
- s = (pl011_state *)qemu_mallocz(sizeof(pl011_state));
- iomemtype = cpu_register_io_memory(0, pl011_readfn,
- pl011_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
- s->irq = irq;
- s->chr = chr;
+ pl011_state *s = FROM_SYSBUS(pl011_state, dev);
+
+ memory_region_init_io(&s->iomem, &pl011_ops, s, "pl011", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
+ sysbus_init_irq(dev, &s->irq);
+ s->id = id;
+ s->chr = qemu_char_get_next_serial();
+
s->read_trigger = 1;
s->ifl = 0x12;
s->cr = 0x300;
s->flags = 0x90;
- if (chr){
- qemu_chr_add_handlers(chr, pl011_can_receive, pl011_receive,
+ if (s->chr) {
+ qemu_chr_add_handlers(s->chr, pl011_can_receive, pl011_receive,
pl011_event, s);
}
- /* ??? Save/restore. */
+ vmstate_register(&dev->qdev, -1, &vmstate_pl011, s);
+ return 0;
+}
+
+static int pl011_arm_init(SysBusDevice *dev)
+{
+ return pl011_init(dev, pl011_id_arm);
+}
+
+static int pl011_luminary_init(SysBusDevice *dev)
+{
+ return pl011_init(dev, pl011_id_luminary);
+}
+
+static void pl011_arm_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = pl011_arm_init;
+}
+
+static TypeInfo pl011_arm_info = {
+ .name = "pl011",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(pl011_state),
+ .class_init = pl011_arm_class_init,
+};
+
+static void pl011_luminary_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = pl011_luminary_init;
+}
+
+static TypeInfo pl011_luminary_info = {
+ .name = "pl011_luminary",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(pl011_state),
+ .class_init = pl011_luminary_class_init,
+};
+
+static void pl011_register_types(void)
+{
+ type_register_static(&pl011_arm_info);
+ type_register_static(&pl011_luminary_info);
}
+type_init(pl011_register_types)
projects / qemu.git / blobdiff