* Copyright (c) 2007 CodeSourcery.
* Written by Paul Brook
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
-#include "hw.h"
-#include "primecell.h"
+#include "sysbus.h"
+#include "ssi.h"
//#define DEBUG_PL022 1
#ifdef DEBUG_PL022
-#define DPRINTF(fmt, args...) \
-do { printf("pl022: " fmt , ##args); } while (0)
-#define BADF(fmt, args...) \
-do { fprintf(stderr, "pl022: error: " fmt , ##args); exit(1);} while (0)
+#define DPRINTF(fmt, ...) \
+do { printf("pl022: " fmt , ## __VA_ARGS__); } while (0)
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__); exit(1);} while (0)
#else
-#define DPRINTF(fmt, args...) do {} while(0)
-#define BADF(fmt, args...) \
-do { fprintf(stderr, "pl022: error: " fmt , ##args);} while (0)
+#define DPRINTF(fmt, ...) do {} while(0)
+#define BADF(fmt, ...) \
+do { fprintf(stderr, "pl022: error: " fmt , ## __VA_ARGS__);} while (0)
#endif
#define PL022_CR1_LBM 0x01
#define PL022_INT_TX 0x08
typedef struct {
- uint32_t base;
+ SysBusDevice busdev;
+ MemoryRegion iomem;
uint32_t cr0;
uint32_t cr1;
uint32_t bitmask;
uint16_t tx_fifo[8];
uint16_t rx_fifo[8];
qemu_irq irq;
- int (*xfer_cb)(void *, int);
- void *opaque;
+ SSIBus *ssi;
} pl022_state;
static const unsigned char pl022_id[8] =
val = s->tx_fifo[i];
if (s->cr1 & PL022_CR1_LBM) {
/* Loopback mode. */
- } else if (s->xfer_cb) {
- val = s->xfer_cb(s->opaque, val);
} else {
- val = 0;
+ val = ssi_transfer(s->ssi, val);
}
s->rx_fifo[o] = val & s->bitmask;
i = (i + 1) & 7;
pl022_update(s);
}
-static uint32_t pl022_read(void *opaque, target_phys_addr_t offset)
+static uint64_t pl022_read(void *opaque, hwaddr offset,
+ unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
int val;
- offset -= s->base;
if (offset >= 0xfe0 && offset < 0x1000) {
return pl022_id[(offset - 0xfe0) >> 2];
}
/* Not implemented. */
return 0;
default:
- cpu_abort (cpu_single_env, "pl022_read: Bad offset %x\n",
- (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl022_read: Bad offset %x\n", (int)offset);
return 0;
}
}
-static void pl022_write(void *opaque, target_phys_addr_t offset,
- uint32_t value)
+static void pl022_write(void *opaque, hwaddr offset,
+ uint64_t value, unsigned size)
{
pl022_state *s = (pl022_state *)opaque;
- offset -= s->base;
switch (offset) {
case 0x00: /* CR0 */
s->cr0 = value;
break;
case 0x08: /* DR */
if (s->tx_fifo_len < 8) {
- DPRINTF("TX %02x\n", value);
+ DPRINTF("TX %02x\n", (unsigned)value);
s->tx_fifo[s->tx_fifo_head] = value & s->bitmask;
s->tx_fifo_head = (s->tx_fifo_head + 1) & 7;
s->tx_fifo_len++;
pl022_update(s);
break;
case 0x20: /* DMACR */
- if (value)
- cpu_abort (cpu_single_env, "pl022: DMA not implemented\n");
+ if (value) {
+ qemu_log_mask(LOG_UNIMP, "pl022: DMA not implemented\n");
+ }
break;
default:
- cpu_abort (cpu_single_env, "pl022_write: Bad offset %x\n",
- (int)offset);
+ qemu_log_mask(LOG_GUEST_ERROR,
+ "pl022_write: Bad offset %x\n", (int)offset);
}
}
s->sr = PL022_SR_TFE | PL022_SR_TNF;
}
-static CPUReadMemoryFunc *pl022_readfn[] = {
- pl022_read,
- pl022_read,
- pl022_read
+static const MemoryRegionOps pl022_ops = {
+ .read = pl022_read,
+ .write = pl022_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
-static CPUWriteMemoryFunc *pl022_writefn[] = {
- pl022_write,
- pl022_write,
- pl022_write
+static const VMStateDescription vmstate_pl022 = {
+ .name = "pl022_ssp",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(cr0, pl022_state),
+ VMSTATE_UINT32(cr1, pl022_state),
+ VMSTATE_UINT32(bitmask, pl022_state),
+ VMSTATE_UINT32(sr, pl022_state),
+ VMSTATE_UINT32(cpsr, pl022_state),
+ VMSTATE_UINT32(is, pl022_state),
+ VMSTATE_UINT32(im, pl022_state),
+ VMSTATE_INT32(tx_fifo_head, pl022_state),
+ VMSTATE_INT32(rx_fifo_head, pl022_state),
+ VMSTATE_INT32(tx_fifo_len, pl022_state),
+ VMSTATE_INT32(rx_fifo_len, pl022_state),
+ VMSTATE_UINT16(tx_fifo[0], pl022_state),
+ VMSTATE_UINT16(rx_fifo[0], pl022_state),
+ VMSTATE_UINT16(tx_fifo[1], pl022_state),
+ VMSTATE_UINT16(rx_fifo[1], pl022_state),
+ VMSTATE_UINT16(tx_fifo[2], pl022_state),
+ VMSTATE_UINT16(rx_fifo[2], pl022_state),
+ VMSTATE_UINT16(tx_fifo[3], pl022_state),
+ VMSTATE_UINT16(rx_fifo[3], pl022_state),
+ VMSTATE_UINT16(tx_fifo[4], pl022_state),
+ VMSTATE_UINT16(rx_fifo[4], pl022_state),
+ VMSTATE_UINT16(tx_fifo[5], pl022_state),
+ VMSTATE_UINT16(rx_fifo[5], pl022_state),
+ VMSTATE_UINT16(tx_fifo[6], pl022_state),
+ VMSTATE_UINT16(rx_fifo[6], pl022_state),
+ VMSTATE_UINT16(tx_fifo[7], pl022_state),
+ VMSTATE_UINT16(rx_fifo[7], pl022_state),
+ VMSTATE_END_OF_LIST()
+ }
};
-void pl022_init(uint32_t base, qemu_irq irq, int (*xfer_cb)(void *, int),
- void * opaque)
+static int pl022_init(SysBusDevice *dev)
{
- int iomemtype;
- pl022_state *s;
+ pl022_state *s = FROM_SYSBUS(pl022_state, dev);
- s = (pl022_state *)qemu_mallocz(sizeof(pl022_state));
- iomemtype = cpu_register_io_memory(0, pl022_readfn,
- pl022_writefn, s);
- cpu_register_physical_memory(base, 0x00001000, iomemtype);
- s->base = base;
- s->irq = irq;
- s->xfer_cb = xfer_cb;
- s->opaque = opaque;
+ memory_region_init_io(&s->iomem, &pl022_ops, s, "pl022", 0x1000);
+ sysbus_init_mmio(dev, &s->iomem);
+ sysbus_init_irq(dev, &s->irq);
+ s->ssi = ssi_create_bus(&dev->qdev, "ssi");
pl022_reset(s);
- /* ??? Save/restore. */
+ vmstate_register(&dev->qdev, -1, &vmstate_pl022, s);
+ return 0;
}
+static void pl022_class_init(ObjectClass *klass, void *data)
+{
+ SysBusDeviceClass *sdc = SYS_BUS_DEVICE_CLASS(klass);
+
+ sdc->init = pl022_init;
+}
+
+static const TypeInfo pl022_info = {
+ .name = "pl022",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(pl022_state),
+ .class_init = pl022_class_init,
+};
+
+static void pl022_register_types(void)
+{
+ type_register_static(&pl022_info);
+}
+type_init(pl022_register_types)
projects / qemu.git / blobdiff