Unbreak SDL on Mac OS X

[qemu.git] / hw / ppc405_boards.c

diff --git a/hw/ppc405_boards.c b/hw/ppc405_boards.c
index 6dd8a5f463932c63ad40a79e87134dac5e4d9bb6..945f0959394a97016660ee7a47b4a6dfd86ed602 100644 (file)
--- a/hw/ppc405_boards.c
+++ b/hw/ppc405_boards.c
@@ -29,9 +29,7 @@
 #include "sysemu.h"
 #include "block.h"
 #include "boards.h"
-
-extern int loglevel;
-extern FILE *logfile;
+#include "qemu-log.h"
 
 #define BIOS_FILENAME "ppc405_rom.bin"
 #undef BIOS_SIZE
@@ -56,7 +54,6 @@ extern FILE *logfile;
  */
 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
 struct ref405ep_fpga_t {
-    uint32_t base;
     uint8_t reg0;
     uint8_t reg1;
 };
@@ -67,7 +64,6 @@ static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
     uint32_t ret;
 
     fpga = opaque;
-    addr -= fpga->base;
     switch (addr) {
     case 0x0:
         ret = fpga->reg0;
@@ -89,7 +85,6 @@ static void ref405ep_fpga_writeb (void *opaque,
     ref405ep_fpga_t *fpga;
 
     fpga = opaque;
-    addr -= fpga->base;
     switch (addr) {
     case 0x0:
         /* Read only */
@@ -134,9 +129,9 @@ static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 static void ref405ep_fpga_writel (void *opaque,
                                   target_phys_addr_t addr, uint32_t value)
 {
-    ref405ep_fpga_writel(opaque, addr, (value >> 24) & 0xFF);
-    ref405ep_fpga_writel(opaque, addr + 1, (value >> 16) & 0xFF);
-    ref405ep_fpga_writel(opaque, addr + 2, (value >> 8) & 0xFF);
+    ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
+    ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
+    ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 }
 
@@ -167,18 +162,15 @@ static void ref405ep_fpga_init (uint32_t base)
     int fpga_memory;
 
     fpga = qemu_mallocz(sizeof(ref405ep_fpga_t));
-    if (fpga != NULL) {
-        fpga->base = base;
-        fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
-                                             ref405ep_fpga_write, fpga);
-        cpu_register_physical_memory(base, 0x00000100, fpga_memory);
-        ref405ep_fpga_reset(fpga);
-        qemu_register_reset(&ref405ep_fpga_reset, fpga);
-    }
+    fpga_memory = cpu_register_io_memory(0, ref405ep_fpga_read,
+                                         ref405ep_fpga_write, fpga);
+    cpu_register_physical_memory(base, 0x00000100, fpga_memory);
+    ref405ep_fpga_reset(fpga);
+    qemu_register_reset(&ref405ep_fpga_reset, fpga);
 }
 
 static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
-                           const char *boot_device, DisplayState *ds,
+                           const char *boot_device,
                            const char *kernel_filename,
                            const char *kernel_cmdline,
                            const char *initrd_filename,
@@ -357,9 +349,10 @@ static void ref405ep_init (ram_addr_t ram_size, int vga_ram_size,
 }
 
 QEMUMachine ref405ep_machine = {
-    "ref405ep",
-    "ref405ep",
-    ref405ep_init,
+    .name = "ref405ep",
+    .desc = "ref405ep",
+    .init = ref405ep_init,
+    .ram_require = (128 * 1024 * 1024 + 4096 + 512 * 1024 + BIOS_SIZE) | RAMSIZE_FIXED,
 };
 
 /*****************************************************************************/
@@ -383,7 +376,6 @@ QEMUMachine ref405ep_machine = {
  */
 typedef struct taihu_cpld_t taihu_cpld_t;
 struct taihu_cpld_t {
-    uint32_t base;
     uint8_t reg0;
     uint8_t reg1;
 };
@@ -394,7 +386,6 @@ static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
     uint32_t ret;
 
     cpld = opaque;
-    addr -= cpld->base;
     switch (addr) {
     case 0x0:
         ret = cpld->reg0;
@@ -416,7 +407,6 @@ static void taihu_cpld_writeb (void *opaque,
     taihu_cpld_t *cpld;
 
     cpld = opaque;
-    addr -= cpld->base;
     switch (addr) {
     case 0x0:
         /* Read only */
@@ -494,18 +484,15 @@ static void taihu_cpld_init (uint32_t base)
     int cpld_memory;
 
     cpld = qemu_mallocz(sizeof(taihu_cpld_t));
-    if (cpld != NULL) {
-        cpld->base = base;
-        cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
-                                             taihu_cpld_write, cpld);
-        cpu_register_physical_memory(base, 0x00000100, cpld_memory);
-        taihu_cpld_reset(cpld);
-        qemu_register_reset(&taihu_cpld_reset, cpld);
-    }
+    cpld_memory = cpu_register_io_memory(0, taihu_cpld_read,
+                                         taihu_cpld_write, cpld);
+    cpu_register_physical_memory(base, 0x00000100, cpld_memory);
+    taihu_cpld_reset(cpld);
+    qemu_register_reset(&taihu_cpld_reset, cpld);
 }
 
 static void taihu_405ep_init(ram_addr_t ram_size, int vga_ram_size,
-                             const char *boot_device, DisplayState *ds,
+                             const char *boot_device,
                              const char *kernel_filename,
                              const char *kernel_cmdline,
                              const char *initrd_filename,
@@ -642,4 +629,5 @@ QEMUMachine taihu_machine = {
     "taihu",
     "taihu",
     taihu_405ep_init,
+    (128 * 1024 * 1024 + 4096 + BIOS_SIZE + 32 * 1024 * 1024) | RAMSIZE_FIXED,
 };