#include "hw.h"
#include "ppc.h"
#include "ppc405.h"
-#include "pc.h"
-#include "qemu-timer.h"
-#include "sysemu.h"
-#include "qemu-log.h"
+#include "serial.h"
+#include "qemu/timer.h"
+#include "sysemu/sysemu.h"
+#include "qemu/log.h"
+#include "exec/address-spaces.h"
#define DEBUG_OPBA
#define DEBUG_SDRAM
#define DEBUG_CLOCKS
//#define DEBUG_CLOCKS_LL
-a_ram_addr ppc405_set_bootinfo (CPUState *env, a_ppc4xx_bd_info *bd,
+ram_addr_t ppc405_set_bootinfo (CPUPPCState *env, ppc4xx_bd_info_t *bd,
uint32_t flags)
{
- a_ram_addr bdloc;
+ ram_addr_t bdloc;
int i, n;
/* We put the bd structure at the top of memory */
if (bd->bi_memsize >= 0x01000000UL)
- bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info);
+ bdloc = 0x01000000UL - sizeof(struct ppc4xx_bd_info_t);
else
- bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info);
- stl_phys(bdloc + 0x00, bd->bi_memstart);
- stl_phys(bdloc + 0x04, bd->bi_memsize);
- stl_phys(bdloc + 0x08, bd->bi_flashstart);
- stl_phys(bdloc + 0x0C, bd->bi_flashsize);
- stl_phys(bdloc + 0x10, bd->bi_flashoffset);
- stl_phys(bdloc + 0x14, bd->bi_sramstart);
- stl_phys(bdloc + 0x18, bd->bi_sramsize);
- stl_phys(bdloc + 0x1C, bd->bi_bootflags);
- stl_phys(bdloc + 0x20, bd->bi_ipaddr);
- for (i = 0; i < 6; i++)
+ bdloc = bd->bi_memsize - sizeof(struct ppc4xx_bd_info_t);
+ stl_be_phys(bdloc + 0x00, bd->bi_memstart);
+ stl_be_phys(bdloc + 0x04, bd->bi_memsize);
+ stl_be_phys(bdloc + 0x08, bd->bi_flashstart);
+ stl_be_phys(bdloc + 0x0C, bd->bi_flashsize);
+ stl_be_phys(bdloc + 0x10, bd->bi_flashoffset);
+ stl_be_phys(bdloc + 0x14, bd->bi_sramstart);
+ stl_be_phys(bdloc + 0x18, bd->bi_sramsize);
+ stl_be_phys(bdloc + 0x1C, bd->bi_bootflags);
+ stl_be_phys(bdloc + 0x20, bd->bi_ipaddr);
+ for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x24 + i, bd->bi_enetaddr[i]);
- stw_phys(bdloc + 0x2A, bd->bi_ethspeed);
- stl_phys(bdloc + 0x2C, bd->bi_intfreq);
- stl_phys(bdloc + 0x30, bd->bi_busfreq);
- stl_phys(bdloc + 0x34, bd->bi_baudrate);
- for (i = 0; i < 4; i++)
+ }
+ stw_be_phys(bdloc + 0x2A, bd->bi_ethspeed);
+ stl_be_phys(bdloc + 0x2C, bd->bi_intfreq);
+ stl_be_phys(bdloc + 0x30, bd->bi_busfreq);
+ stl_be_phys(bdloc + 0x34, bd->bi_baudrate);
+ for (i = 0; i < 4; i++) {
stb_phys(bdloc + 0x38 + i, bd->bi_s_version[i]);
- for (i = 0; i < 32; i++)
- stb_phys(bdloc + 0x3C + i, bd->bi_s_version[i]);
- stl_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
- stl_phys(bdloc + 0x60, bd->bi_pci_busfreq);
- for (i = 0; i < 6; i++)
+ }
+ for (i = 0; i < 32; i++) {
+ stb_phys(bdloc + 0x3C + i, bd->bi_r_version[i]);
+ }
+ stl_be_phys(bdloc + 0x5C, bd->bi_plb_busfreq);
+ stl_be_phys(bdloc + 0x60, bd->bi_pci_busfreq);
+ for (i = 0; i < 6; i++) {
stb_phys(bdloc + 0x64 + i, bd->bi_pci_enetaddr[i]);
+ }
n = 0x6A;
if (flags & 0x00000001) {
for (i = 0; i < 6; i++)
stb_phys(bdloc + n++, bd->bi_pci_enetaddr2[i]);
}
- stl_phys(bdloc + n, bd->bi_opbfreq);
+ stl_be_phys(bdloc + n, bd->bi_opbfreq);
n += 4;
for (i = 0; i < 2; i++) {
- stl_phys(bdloc + n, bd->bi_iic_fast[i]);
+ stl_be_phys(bdloc + n, bd->bi_iic_fast[i]);
n += 4;
}
PLB0_ACR = 0x087,
};
-typedef struct ppc4xx_plb a_ppc4xx_plb;
-struct ppc4xx_plb {
+typedef struct ppc4xx_plb_t ppc4xx_plb_t;
+struct ppc4xx_plb_t {
uint32_t acr;
uint32_t bear;
uint32_t besr;
};
-static target_ulong dcr_read_plb (void *opaque, int dcrn)
+static uint32_t dcr_read_plb (void *opaque, int dcrn)
{
- a_ppc4xx_plb *plb;
- target_ulong ret;
+ ppc4xx_plb_t *plb;
+ uint32_t ret;
plb = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_plb (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_plb (void *opaque, int dcrn, uint32_t val)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
plb = opaque;
switch (dcrn) {
static void ppc4xx_plb_reset (void *opaque)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
plb = opaque;
plb->acr = 0x00000000;
plb->besr = 0x00000000;
}
-static void ppc4xx_plb_init(CPUState *env)
+static void ppc4xx_plb_init(CPUPPCState *env)
{
- a_ppc4xx_plb *plb;
+ ppc4xx_plb_t *plb;
- plb = qemu_mallocz(sizeof(a_ppc4xx_plb));
+ plb = g_malloc0(sizeof(ppc4xx_plb_t));
ppc_dcr_register(env, PLB0_ACR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BEAR, plb, &dcr_read_plb, &dcr_write_plb);
ppc_dcr_register(env, PLB0_BESR, plb, &dcr_read_plb, &dcr_write_plb);
- ppc4xx_plb_reset(plb);
qemu_register_reset(ppc4xx_plb_reset, plb);
}
POB0_BEAR = 0x0A4,
};
-typedef struct ppc4xx_pob a_ppc4xx_pob;
-struct ppc4xx_pob {
+typedef struct ppc4xx_pob_t ppc4xx_pob_t;
+struct ppc4xx_pob_t {
uint32_t bear;
- uint32_t besr[2];
+ uint32_t besr0;
+ uint32_t besr1;
};
-static target_ulong dcr_read_pob (void *opaque, int dcrn)
+static uint32_t dcr_read_pob (void *opaque, int dcrn)
{
- a_ppc4xx_pob *pob;
- target_ulong ret;
+ ppc4xx_pob_t *pob;
+ uint32_t ret;
pob = opaque;
switch (dcrn) {
ret = pob->bear;
break;
case POB0_BESR0:
+ ret = pob->besr0;
+ break;
case POB0_BESR1:
- ret = pob->besr[dcrn - POB0_BESR0];
+ ret = pob->besr1;
break;
default:
/* Avoid gcc warning */
return ret;
}
-static void dcr_write_pob (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_pob (void *opaque, int dcrn, uint32_t val)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
pob = opaque;
switch (dcrn) {
/* Read only */
break;
case POB0_BESR0:
+ /* Write-clear */
+ pob->besr0 &= ~val;
+ break;
case POB0_BESR1:
/* Write-clear */
- pob->besr[dcrn - POB0_BESR0] &= ~val;
+ pob->besr1 &= ~val;
break;
}
}
static void ppc4xx_pob_reset (void *opaque)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
pob = opaque;
/* No error */
pob->bear = 0x00000000;
- pob->besr[0] = 0x0000000;
- pob->besr[1] = 0x0000000;
+ pob->besr0 = 0x0000000;
+ pob->besr1 = 0x0000000;
}
-static void ppc4xx_pob_init(CPUState *env)
+static void ppc4xx_pob_init(CPUPPCState *env)
{
- a_ppc4xx_pob *pob;
+ ppc4xx_pob_t *pob;
- pob = qemu_mallocz(sizeof(a_ppc4xx_pob));
+ pob = g_malloc0(sizeof(ppc4xx_pob_t));
ppc_dcr_register(env, POB0_BEAR, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR0, pob, &dcr_read_pob, &dcr_write_pob);
ppc_dcr_register(env, POB0_BESR1, pob, &dcr_read_pob, &dcr_write_pob);
qemu_register_reset(ppc4xx_pob_reset, pob);
- ppc4xx_pob_reset(pob);
}
/*****************************************************************************/
/* OPB arbitrer */
-typedef struct ppc4xx_opba a_ppc4xx_opba;
-struct ppc4xx_opba {
+typedef struct ppc4xx_opba_t ppc4xx_opba_t;
+struct ppc4xx_opba_t {
+ MemoryRegion io;
uint8_t cr;
uint8_t pr;
};
-static uint32_t opba_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readb (void *opaque, hwaddr addr)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
uint32_t ret;
#ifdef DEBUG_OPBA
}
static void opba_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
}
}
-static uint32_t opba_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void opba_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
opba_writeb(opaque, addr + 1, value);
}
-static uint32_t opba_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t opba_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void opba_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_OPBA
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
opba_writeb(opaque, addr + 1, value >> 16);
}
-static CPUReadMemoryFunc * const opba_read[] = {
- &opba_readb,
- &opba_readw,
- &opba_readl,
-};
-
-static CPUWriteMemoryFunc * const opba_write[] = {
- &opba_writeb,
- &opba_writew,
- &opba_writel,
+static const MemoryRegionOps opba_ops = {
+ .old_mmio = {
+ .read = { opba_readb, opba_readw, opba_readl, },
+ .write = { opba_writeb, opba_writew, opba_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_opba_reset (void *opaque)
{
- a_ppc4xx_opba *opba;
+ ppc4xx_opba_t *opba;
opba = opaque;
opba->cr = 0x00; /* No dynamic priorities - park disabled */
opba->pr = 0x11;
}
-static void ppc4xx_opba_init(a_target_phys_addr base)
+static void ppc4xx_opba_init(hwaddr base)
{
- a_ppc4xx_opba *opba;
- int io;
+ ppc4xx_opba_t *opba;
- opba = qemu_mallocz(sizeof(a_ppc4xx_opba));
+ opba = g_malloc0(sizeof(ppc4xx_opba_t));
#ifdef DEBUG_OPBA
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(opba_read, opba_write, opba);
- cpu_register_physical_memory(base, 0x002, io);
- ppc4xx_opba_reset(opba);
+ memory_region_init_io(&opba->io, &opba_ops, opba, "opba", 0x002);
+ memory_region_add_subregion(get_system_memory(), base, &opba->io);
qemu_register_reset(ppc4xx_opba_reset, opba);
}
/*****************************************************************************/
/* Peripheral controller */
-typedef struct ppc4xx_ebc a_ppc4xx_ebc;
-struct ppc4xx_ebc {
+typedef struct ppc4xx_ebc_t ppc4xx_ebc_t;
+struct ppc4xx_ebc_t {
uint32_t addr;
uint32_t bcr[8];
uint32_t bap[8];
EBC0_CFGDATA = 0x013,
};
-static target_ulong dcr_read_ebc (void *opaque, int dcrn)
+static uint32_t dcr_read_ebc (void *opaque, int dcrn)
{
- a_ppc4xx_ebc *ebc;
- target_ulong ret;
+ ppc4xx_ebc_t *ebc;
+ uint32_t ret;
ebc = opaque;
switch (dcrn) {
ret = 0x00000000;
break;
}
+ break;
default:
ret = 0x00000000;
break;
return ret;
}
-static void dcr_write_ebc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ebc (void *opaque, int dcrn, uint32_t val)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
ebc = opaque;
switch (dcrn) {
static void ebc_reset (void *opaque)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
int i;
ebc = opaque;
ebc->cfg = 0x80400000;
}
-static void ppc405_ebc_init(CPUState *env)
+static void ppc405_ebc_init(CPUPPCState *env)
{
- a_ppc4xx_ebc *ebc;
+ ppc4xx_ebc_t *ebc;
- ebc = qemu_mallocz(sizeof(a_ppc4xx_ebc));
- ebc_reset(ebc);
+ ebc = g_malloc0(sizeof(ppc4xx_ebc_t));
qemu_register_reset(&ebc_reset, ebc);
ppc_dcr_register(env, EBC0_CFGADDR,
ebc, &dcr_read_ebc, &dcr_write_ebc);
DMA0_POL = 0x126,
};
-typedef struct ppc405_dma a_ppc405_dma;
-struct ppc405_dma {
+typedef struct ppc405_dma_t ppc405_dma_t;
+struct ppc405_dma_t {
qemu_irq irqs[4];
uint32_t cr[4];
uint32_t ct[4];
uint32_t pol;
};
-static target_ulong dcr_read_dma (void *opaque, int dcrn)
+static uint32_t dcr_read_dma (void *opaque, int dcrn)
{
- a_ppc405_dma *dma;
-
- dma = opaque;
-
return 0;
}
-static void dcr_write_dma (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_dma (void *opaque, int dcrn, uint32_t val)
{
- a_ppc405_dma *dma;
-
- dma = opaque;
}
static void ppc405_dma_reset (void *opaque)
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
int i;
dma = opaque;
dma->pol = 0x00000000;
}
-static void ppc405_dma_init(CPUState *env, qemu_irq irqs[4])
+static void ppc405_dma_init(CPUPPCState *env, qemu_irq irqs[4])
{
- a_ppc405_dma *dma;
+ ppc405_dma_t *dma;
- dma = qemu_mallocz(sizeof(a_ppc405_dma));
+ dma = g_malloc0(sizeof(ppc405_dma_t));
memcpy(dma->irqs, irqs, 4 * sizeof(qemu_irq));
- ppc405_dma_reset(dma);
qemu_register_reset(&ppc405_dma_reset, dma);
ppc_dcr_register(env, DMA0_CR0,
dma, &dcr_read_dma, &dcr_write_dma);
/*****************************************************************************/
/* GPIO */
-typedef struct ppc405_gpio a_ppc405_gpio;
-struct ppc405_gpio {
+typedef struct ppc405_gpio_t ppc405_gpio_t;
+struct ppc405_gpio_t {
+ MemoryRegion io;
uint32_t or;
uint32_t tcr;
uint32_t osrh;
uint32_t isr1l;
};
-static uint32_t ppc405_gpio_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readb (void *opaque, hwaddr addr)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
}
static void ppc405_gpio_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
-static uint32_t ppc405_gpio_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readw (void *opaque, hwaddr addr)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
}
static void ppc405_gpio_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
-static uint32_t ppc405_gpio_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc405_gpio_readl (void *opaque, hwaddr addr)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
#endif
}
static void ppc405_gpio_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
#ifdef DEBUG_GPIO
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
value);
#endif
}
-static CPUReadMemoryFunc * const ppc405_gpio_read[] = {
- &ppc405_gpio_readb,
- &ppc405_gpio_readw,
- &ppc405_gpio_readl,
-};
-
-static CPUWriteMemoryFunc * const ppc405_gpio_write[] = {
- &ppc405_gpio_writeb,
- &ppc405_gpio_writew,
- &ppc405_gpio_writel,
+static const MemoryRegionOps ppc405_gpio_ops = {
+ .old_mmio = {
+ .read = { ppc405_gpio_readb, ppc405_gpio_readw, ppc405_gpio_readl, },
+ .write = { ppc405_gpio_writeb, ppc405_gpio_writew, ppc405_gpio_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc405_gpio_reset (void *opaque)
{
- a_ppc405_gpio *gpio;
-
- gpio = opaque;
}
-static void ppc405_gpio_init(a_target_phys_addr base)
+static void ppc405_gpio_init(hwaddr base)
{
- a_ppc405_gpio *gpio;
- int io;
+ ppc405_gpio_t *gpio;
- gpio = qemu_mallocz(sizeof(a_ppc405_gpio));
+ gpio = g_malloc0(sizeof(ppc405_gpio_t));
#ifdef DEBUG_GPIO
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(ppc405_gpio_read, ppc405_gpio_write, gpio);
- cpu_register_physical_memory(base, 0x038, io);
- ppc405_gpio_reset(gpio);
+ memory_region_init_io(&gpio->io, &ppc405_gpio_ops, gpio, "pgio", 0x038);
+ memory_region_add_subregion(get_system_memory(), base, &gpio->io);
qemu_register_reset(&ppc405_gpio_reset, gpio);
}
OCM0_DSACNTL = 0x01B,
};
-typedef struct ppc405_ocm a_ppc405_ocm;
-struct ppc405_ocm {
- target_ulong offset;
+typedef struct ppc405_ocm_t ppc405_ocm_t;
+struct ppc405_ocm_t {
+ MemoryRegion ram;
+ MemoryRegion isarc_ram;
+ MemoryRegion dsarc_ram;
uint32_t isarc;
uint32_t isacntl;
uint32_t dsarc;
uint32_t dsacntl;
};
-static void ocm_update_mappings (a_ppc405_ocm *ocm,
+static void ocm_update_mappings (ppc405_ocm_t *ocm,
uint32_t isarc, uint32_t isacntl,
uint32_t dsarc, uint32_t dsacntl)
{
if (ocm->isacntl & 0x80000000) {
/* Unmap previously assigned memory region */
printf("OCM unmap ISA %08" PRIx32 "\n", ocm->isarc);
- cpu_register_physical_memory(ocm->isarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(), &ocm->isarc_ram);
}
if (isacntl & 0x80000000) {
/* Map new instruction memory region */
#ifdef DEBUG_OCM
printf("OCM map ISA %08" PRIx32 "\n", isarc);
#endif
- cpu_register_physical_memory(isarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), isarc,
+ &ocm->isarc_ram);
}
}
if (ocm->dsarc != dsarc ||
#ifdef DEBUG_OCM
printf("OCM unmap DSA %08" PRIx32 "\n", ocm->dsarc);
#endif
- cpu_register_physical_memory(ocm->dsarc, 0x04000000,
- IO_MEM_UNASSIGNED);
+ memory_region_del_subregion(get_system_memory(),
+ &ocm->dsarc_ram);
}
}
if (dsacntl & 0x80000000) {
#ifdef DEBUG_OCM
printf("OCM map DSA %08" PRIx32 "\n", dsarc);
#endif
- cpu_register_physical_memory(dsarc, 0x04000000,
- ocm->offset | IO_MEM_RAM);
+ memory_region_add_subregion(get_system_memory(), dsarc,
+ &ocm->dsarc_ram);
}
}
}
}
-static target_ulong dcr_read_ocm (void *opaque, int dcrn)
+static uint32_t dcr_read_ocm (void *opaque, int dcrn)
{
- a_ppc405_ocm *ocm;
- target_ulong ret;
+ ppc405_ocm_t *ocm;
+ uint32_t ret;
ocm = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_ocm (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_ocm (void *opaque, int dcrn, uint32_t val)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
static void ocm_reset (void *opaque)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
uint32_t isarc, dsarc, isacntl, dsacntl;
ocm = opaque;
ocm->dsacntl = dsacntl;
}
-static void ppc405_ocm_init(CPUState *env)
+static void ppc405_ocm_init(CPUPPCState *env)
{
- a_ppc405_ocm *ocm;
+ ppc405_ocm_t *ocm;
- ocm = qemu_mallocz(sizeof(a_ppc405_ocm));
- ocm->offset = qemu_ram_alloc(4096);
- ocm_reset(ocm);
+ ocm = g_malloc0(sizeof(ppc405_ocm_t));
+ /* XXX: Size is 4096 or 0x04000000 */
+ memory_region_init_ram(&ocm->isarc_ram, "ppc405.ocm", 4096);
+ vmstate_register_ram_global(&ocm->isarc_ram);
+ memory_region_init_alias(&ocm->dsarc_ram, "ppc405.dsarc", &ocm->isarc_ram,
+ 0, 4096);
qemu_register_reset(&ocm_reset, ocm);
ppc_dcr_register(env, OCM0_ISARC,
ocm, &dcr_read_ocm, &dcr_write_ocm);
/*****************************************************************************/
/* I2C controller */
-typedef struct ppc4xx_i2c a_ppc4xx_i2c;
-struct ppc4xx_i2c {
+typedef struct ppc4xx_i2c_t ppc4xx_i2c_t;
+struct ppc4xx_i2c_t {
qemu_irq irq;
+ MemoryRegion iomem;
uint8_t mdata;
uint8_t lmadr;
uint8_t hmadr;
uint8_t directcntl;
};
-static uint32_t ppc4xx_i2c_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readb (void *opaque, hwaddr addr)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
uint32_t ret;
#ifdef DEBUG_I2C
}
static void ppc4xx_i2c_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
}
}
-static uint32_t ppc4xx_i2c_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readw (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ppc4xx_i2c_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
ppc4xx_i2c_writeb(opaque, addr + 1, value);
}
-static uint32_t ppc4xx_i2c_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_i2c_readl (void *opaque, hwaddr addr)
{
uint32_t ret;
}
static void ppc4xx_i2c_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
ppc4xx_i2c_writeb(opaque, addr + 3, value);
}
-static CPUReadMemoryFunc * const i2c_read[] = {
- &ppc4xx_i2c_readb,
- &ppc4xx_i2c_readw,
- &ppc4xx_i2c_readl,
-};
-
-static CPUWriteMemoryFunc * const i2c_write[] = {
- &ppc4xx_i2c_writeb,
- &ppc4xx_i2c_writew,
- &ppc4xx_i2c_writel,
+static const MemoryRegionOps i2c_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_i2c_readb, ppc4xx_i2c_readw, ppc4xx_i2c_readl, },
+ .write = { ppc4xx_i2c_writeb, ppc4xx_i2c_writew, ppc4xx_i2c_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_i2c_reset (void *opaque)
{
- a_ppc4xx_i2c *i2c;
+ ppc4xx_i2c_t *i2c;
i2c = opaque;
i2c->mdata = 0x00;
i2c->directcntl = 0x0F;
}
-static void ppc405_i2c_init(a_target_phys_addr base, qemu_irq irq)
+static void ppc405_i2c_init(hwaddr base, qemu_irq irq)
{
- a_ppc4xx_i2c *i2c;
- int io;
+ ppc4xx_i2c_t *i2c;
- i2c = qemu_mallocz(sizeof(a_ppc4xx_i2c));
+ i2c = g_malloc0(sizeof(ppc4xx_i2c_t));
i2c->irq = irq;
#ifdef DEBUG_I2C
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(i2c_read, i2c_write, i2c);
- cpu_register_physical_memory(base, 0x011, io);
- ppc4xx_i2c_reset(i2c);
+ memory_region_init_io(&i2c->iomem, &i2c_ops, i2c, "i2c", 0x011);
+ memory_region_add_subregion(get_system_memory(), base, &i2c->iomem);
qemu_register_reset(ppc4xx_i2c_reset, i2c);
}
/*****************************************************************************/
/* General purpose timers */
-typedef struct ppc4xx_gpt a_ppc4xx_gpt;
-struct ppc4xx_gpt {
+typedef struct ppc4xx_gpt_t ppc4xx_gpt_t;
+struct ppc4xx_gpt_t {
+ MemoryRegion iomem;
int64_t tb_offset;
uint32_t tb_freq;
struct QEMUTimer *timer;
uint32_t mask[5];
};
-static uint32_t ppc4xx_gpt_readb (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readb (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc4xx_gpt_writeb (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
/* XXX: generate a bus fault */
}
-static uint32_t ppc4xx_gpt_readw (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readw (void *opaque, hwaddr addr)
{
#ifdef DEBUG_GPT
printf("%s: addr " TARGET_FMT_plx "\n", __func__, addr);
}
static void ppc4xx_gpt_writew (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
#ifdef DEBUG_I2C
printf("%s: addr " TARGET_FMT_plx " val %08" PRIx32 "\n", __func__, addr,
/* XXX: generate a bus fault */
}
-static int ppc4xx_gpt_compare (a_ppc4xx_gpt *gpt, int n)
+static int ppc4xx_gpt_compare (ppc4xx_gpt_t *gpt, int n)
{
/* XXX: TODO */
return 0;
}
-static void ppc4xx_gpt_set_output (a_ppc4xx_gpt *gpt, int n, int level)
+static void ppc4xx_gpt_set_output (ppc4xx_gpt_t *gpt, int n, int level)
{
/* XXX: TODO */
}
-static void ppc4xx_gpt_set_outputs (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_set_outputs (ppc4xx_gpt_t *gpt)
{
uint32_t mask;
int i;
}
}
-static void ppc4xx_gpt_set_irqs (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_set_irqs (ppc4xx_gpt_t *gpt)
{
uint32_t mask;
int i;
}
}
-static void ppc4xx_gpt_compute_timer (a_ppc4xx_gpt *gpt)
+static void ppc4xx_gpt_compute_timer (ppc4xx_gpt_t *gpt)
{
/* XXX: TODO */
}
-static uint32_t ppc4xx_gpt_readl (void *opaque, a_target_phys_addr addr)
+static uint32_t ppc4xx_gpt_readl (void *opaque, hwaddr addr)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
uint32_t ret;
int idx;
switch (addr) {
case 0x00:
/* Time base counter */
- ret = muldiv64(qemu_get_clock(vm_clock) + gpt->tb_offset,
+ ret = muldiv64(qemu_get_clock_ns(vm_clock) + gpt->tb_offset,
gpt->tb_freq, get_ticks_per_sec());
break;
case 0x10:
}
static void ppc4xx_gpt_writel (void *opaque,
- a_target_phys_addr addr, uint32_t value)
+ hwaddr addr, uint32_t value)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int idx;
#ifdef DEBUG_I2C
case 0x00:
/* Time base counter */
gpt->tb_offset = muldiv64(value, get_ticks_per_sec(), gpt->tb_freq)
- - qemu_get_clock(vm_clock);
+ - qemu_get_clock_ns(vm_clock);
ppc4xx_gpt_compute_timer(gpt);
break;
case 0x10:
}
}
-static CPUReadMemoryFunc * const gpt_read[] = {
- &ppc4xx_gpt_readb,
- &ppc4xx_gpt_readw,
- &ppc4xx_gpt_readl,
-};
-
-static CPUWriteMemoryFunc * const gpt_write[] = {
- &ppc4xx_gpt_writeb,
- &ppc4xx_gpt_writew,
- &ppc4xx_gpt_writel,
+static const MemoryRegionOps gpt_ops = {
+ .old_mmio = {
+ .read = { ppc4xx_gpt_readb, ppc4xx_gpt_readw, ppc4xx_gpt_readl, },
+ .write = { ppc4xx_gpt_writeb, ppc4xx_gpt_writew, ppc4xx_gpt_writel, },
+ },
+ .endianness = DEVICE_NATIVE_ENDIAN,
};
static void ppc4xx_gpt_cb (void *opaque)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
gpt = opaque;
ppc4xx_gpt_set_irqs(gpt);
static void ppc4xx_gpt_reset (void *opaque)
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int i;
gpt = opaque;
}
}
-static void ppc4xx_gpt_init(a_target_phys_addr base, qemu_irq irqs[5])
+static void ppc4xx_gpt_init(hwaddr base, qemu_irq irqs[5])
{
- a_ppc4xx_gpt *gpt;
+ ppc4xx_gpt_t *gpt;
int i;
- int io;
- gpt = qemu_mallocz(sizeof(a_ppc4xx_gpt));
+ gpt = g_malloc0(sizeof(ppc4xx_gpt_t));
for (i = 0; i < 5; i++) {
gpt->irqs[i] = irqs[i];
}
- gpt->timer = qemu_new_timer(vm_clock, &ppc4xx_gpt_cb, gpt);
+ gpt->timer = qemu_new_timer_ns(vm_clock, &ppc4xx_gpt_cb, gpt);
#ifdef DEBUG_GPT
printf("%s: offset " TARGET_FMT_plx "\n", __func__, base);
#endif
- io = cpu_register_io_memory(gpt_read, gpt_write, gpt);
- cpu_register_physical_memory(base, 0x0d4, io);
+ memory_region_init_io(&gpt->iomem, &gpt_ops, gpt, "gpt", 0x0d4);
+ memory_region_add_subregion(get_system_memory(), base, &gpt->iomem);
qemu_register_reset(ppc4xx_gpt_reset, gpt);
- ppc4xx_gpt_reset(gpt);
}
/*****************************************************************************/
MAL0_RCBS1 = 0x1E1,
};
-typedef struct ppc40x_mal a_ppc40x_mal;
-struct ppc40x_mal {
+typedef struct ppc40x_mal_t ppc40x_mal_t;
+struct ppc40x_mal_t {
qemu_irq irqs[4];
uint32_t cfg;
uint32_t esr;
static void ppc40x_mal_reset (void *opaque);
-static target_ulong dcr_read_mal (void *opaque, int dcrn)
+static uint32_t dcr_read_mal (void *opaque, int dcrn)
{
- a_ppc40x_mal *mal;
- target_ulong ret;
+ ppc40x_mal_t *mal;
+ uint32_t ret;
mal = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_mal (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_mal (void *opaque, int dcrn, uint32_t val)
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
int idx;
mal = opaque;
static void ppc40x_mal_reset (void *opaque)
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
mal = opaque;
mal->cfg = 0x0007C000;
mal->txeobisr = 0x00000000;
}
-static void ppc405_mal_init(CPUState *env, qemu_irq irqs[4])
+static void ppc405_mal_init(CPUPPCState *env, qemu_irq irqs[4])
{
- a_ppc40x_mal *mal;
+ ppc40x_mal_t *mal;
int i;
- mal = qemu_mallocz(sizeof(a_ppc40x_mal));
+ mal = g_malloc0(sizeof(ppc40x_mal_t));
for (i = 0; i < 4; i++)
mal->irqs[i] = irqs[i];
- ppc40x_mal_reset(mal);
qemu_register_reset(&ppc40x_mal_reset, mal);
ppc_dcr_register(env, MAL0_CFG,
mal, &dcr_read_mal, &dcr_write_mal);
/*****************************************************************************/
/* SPR */
-void ppc40x_core_reset (CPUState *env)
+void ppc40x_core_reset (CPUPPCState *env)
{
target_ulong dbsr;
printf("Reset PowerPC core\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_ppc_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
dbsr |= 0x00000100;
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_chip_reset (CPUState *env)
+void ppc40x_chip_reset (CPUPPCState *env)
{
target_ulong dbsr;
printf("Reset PowerPC chip\n");
- env->interrupt_request |= CPU_INTERRUPT_EXITTB;
- /* XXX: TOFIX */
-#if 0
- cpu_ppc_reset(env);
-#else
- qemu_system_reset_request();
-#endif
+ cpu_interrupt(env, CPU_INTERRUPT_RESET);
/* XXX: TODO reset all internal peripherals */
dbsr = env->spr[SPR_40x_DBSR];
dbsr &= ~0x00000300;
env->spr[SPR_40x_DBSR] = dbsr;
}
-void ppc40x_system_reset (CPUState *env)
+void ppc40x_system_reset (CPUPPCState *env)
{
printf("Reset PowerPC system\n");
qemu_system_reset_request();
}
-void store_40x_dbcr0 (CPUState *env, uint32_t val)
+void store_40x_dbcr0 (CPUPPCState *env, uint32_t val)
{
switch ((val >> 28) & 0x3) {
case 0x0:
PPC405CR_CLK_NB = 7,
};
-typedef struct ppc405cr_cpc a_ppc405cr_cpc;
-struct ppc405cr_cpc {
- a_clk_setup clk_setup[PPC405CR_CLK_NB];
+typedef struct ppc405cr_cpc_t ppc405cr_cpc_t;
+struct ppc405cr_cpc_t {
+ clk_setup_t clk_setup[PPC405CR_CLK_NB];
uint32_t sysclk;
uint32_t psr;
uint32_t cr0;
uint32_t fr;
};
-static void ppc405cr_clk_setup (a_ppc405cr_cpc *cpc)
+static void ppc405cr_clk_setup (ppc405cr_cpc_t *cpc)
{
uint64_t VCO_out, PLL_out;
uint32_t CPU_clk, TMR_clk, SDRAM_clk, PLB_clk, OPB_clk, EXT_clk, UART_clk;
clk_setup(&cpc->clk_setup[PPC405CR_UART_CLK], UART_clk);
}
-static target_ulong dcr_read_crcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_crcpc (void *opaque, int dcrn)
{
- a_ppc405cr_cpc *cpc;
- target_ulong ret;
+ ppc405cr_cpc_t *cpc;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_crcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_crcpc (void *opaque, int dcrn, uint32_t val)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
cpc = opaque;
switch (dcrn) {
static void ppc405cr_cpc_reset (void *opaque)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
int D;
cpc = opaque;
ppc405cr_clk_setup(cpc);
}
-static void ppc405cr_clk_init (a_ppc405cr_cpc *cpc)
+static void ppc405cr_clk_init (ppc405cr_cpc_t *cpc)
{
int D;
cpc->psr |= D << 17;
}
-static void ppc405cr_cpc_init (CPUState *env, a_clk_setup clk_setup[7],
+static void ppc405cr_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[7],
uint32_t sysclk)
{
- a_ppc405cr_cpc *cpc;
+ ppc405cr_cpc_t *cpc;
- cpc = qemu_mallocz(sizeof(a_ppc405cr_cpc));
+ cpc = g_malloc0(sizeof(ppc405cr_cpc_t));
memcpy(cpc->clk_setup, clk_setup,
- PPC405CR_CLK_NB * sizeof(a_clk_setup));
+ PPC405CR_CLK_NB * sizeof(clk_setup_t));
cpc->sysclk = sysclk;
cpc->jtagid = 0x42051049;
ppc_dcr_register(env, PPC405CR_CPC0_PSR, cpc,
&dcr_read_crcpc, &dcr_write_crcpc);
ppc405cr_clk_init(cpc);
qemu_register_reset(ppc405cr_cpc_reset, cpc);
- ppc405cr_cpc_reset(cpc);
}
-CPUState *ppc405cr_init (a_target_phys_addr ram_bases[4],
- a_target_phys_addr ram_sizes[4],
- uint32_t sysclk, qemu_irq **picp,
- int do_init)
+CPUPPCState *ppc405cr_init(MemoryRegion *address_space_mem,
+ MemoryRegion ram_memories[4],
+ hwaddr ram_bases[4],
+ hwaddr ram_sizes[4],
+ uint32_t sysclk, qemu_irq **picp,
+ int do_init)
{
- a_clk_setup clk_setup[PPC405CR_CLK_NB];
+ clk_setup_t clk_setup[PPC405CR_CLK_NB];
qemu_irq dma_irqs[4];
- CPUState *env;
+ PowerPCCPU *cpu;
+ CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
- env = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
+ cpu = ppc4xx_init("405cr", &clk_setup[PPC405CR_CPU_CLK],
&clk_setup[PPC405CR_TMR_CLK], sysclk);
+ env = &cpu->env;
/* Memory mapped devices registers */
/* PLB arbitrer */
ppc4xx_plb_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
/* Universal interrupt controller */
- irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
+ irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] =
pic = ppcuic_init(env, irqs, 0x0C0, 0, 1);
*picp = pic;
/* SDRAM controller */
- ppc4xx_sdram_init(env, pic[14], 1, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[14], 1, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
ppc405_dma_init(env, dma_irqs);
/* Serial ports */
if (serial_hds[0] != NULL) {
- serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
+ PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
+ DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
- serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
+ PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
+ DEVICE_BIG_ENDIAN);
}
/* IIC controller */
ppc405_i2c_init(0xef600500, pic[2]);
PPC405EP_CLK_NB = 8,
};
-typedef struct ppc405ep_cpc a_ppc405ep_cpc;
-struct ppc405ep_cpc {
+typedef struct ppc405ep_cpc_t ppc405ep_cpc_t;
+struct ppc405ep_cpc_t {
uint32_t sysclk;
- a_clk_setup clk_setup[PPC405EP_CLK_NB];
+ clk_setup_t clk_setup[PPC405EP_CLK_NB];
uint32_t boot;
uint32_t epctl;
uint32_t pllmr[2];
uint32_t sr;
};
-static void ppc405ep_compute_clocks (a_ppc405ep_cpc *cpc)
+static void ppc405ep_compute_clocks (ppc405ep_cpc_t *cpc)
{
uint32_t CPU_clk, PLB_clk, OPB_clk, EBC_clk, MAL_clk, PCI_clk;
uint32_t UART0_clk, UART1_clk;
clk_setup(&cpc->clk_setup[PPC405EP_UART1_CLK], UART1_clk);
}
-static target_ulong dcr_read_epcpc (void *opaque, int dcrn)
+static uint32_t dcr_read_epcpc (void *opaque, int dcrn)
{
- a_ppc405ep_cpc *cpc;
- target_ulong ret;
+ ppc405ep_cpc_t *cpc;
+ uint32_t ret;
cpc = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_epcpc (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_epcpc (void *opaque, int dcrn, uint32_t val)
{
- a_ppc405ep_cpc *cpc;
+ ppc405ep_cpc_t *cpc;
cpc = opaque;
switch (dcrn) {
static void ppc405ep_cpc_reset (void *opaque)
{
- a_ppc405ep_cpc *cpc = opaque;
+ ppc405ep_cpc_t *cpc = opaque;
cpc->boot = 0x00000010; /* Boot from PCI - IIC EEPROM disabled */
cpc->epctl = 0x00000000;
}
/* XXX: sysclk should be between 25 and 100 MHz */
-static void ppc405ep_cpc_init (CPUState *env, a_clk_setup clk_setup[8],
+static void ppc405ep_cpc_init (CPUPPCState *env, clk_setup_t clk_setup[8],
uint32_t sysclk)
{
- a_ppc405ep_cpc *cpc;
+ ppc405ep_cpc_t *cpc;
- cpc = qemu_mallocz(sizeof(a_ppc405ep_cpc));
+ cpc = g_malloc0(sizeof(ppc405ep_cpc_t));
memcpy(cpc->clk_setup, clk_setup,
- PPC405EP_CLK_NB * sizeof(a_clk_setup));
+ PPC405EP_CLK_NB * sizeof(clk_setup_t));
cpc->jtagid = 0x20267049;
cpc->sysclk = sysclk;
- ppc405ep_cpc_reset(cpc);
qemu_register_reset(&ppc405ep_cpc_reset, cpc);
ppc_dcr_register(env, PPC405EP_CPC0_BOOT, cpc,
&dcr_read_epcpc, &dcr_write_epcpc);
#endif
}
-CPUState *ppc405ep_init (a_target_phys_addr ram_bases[2],
- a_target_phys_addr ram_sizes[2],
- uint32_t sysclk, qemu_irq **picp,
- int do_init)
+CPUPPCState *ppc405ep_init(MemoryRegion *address_space_mem,
+ MemoryRegion ram_memories[2],
+ hwaddr ram_bases[2],
+ hwaddr ram_sizes[2],
+ uint32_t sysclk, qemu_irq **picp,
+ int do_init)
{
- a_clk_setup clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
+ clk_setup_t clk_setup[PPC405EP_CLK_NB], tlb_clk_setup;
qemu_irq dma_irqs[4], gpt_irqs[5], mal_irqs[4];
- CPUState *env;
+ PowerPCCPU *cpu;
+ CPUPPCState *env;
qemu_irq *pic, *irqs;
memset(clk_setup, 0, sizeof(clk_setup));
/* init CPUs */
- env = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
+ cpu = ppc4xx_init("405ep", &clk_setup[PPC405EP_CPU_CLK],
&tlb_clk_setup, sysclk);
+ env = &cpu->env;
clk_setup[PPC405EP_CPU_CLK].cb = tlb_clk_setup.cb;
clk_setup[PPC405EP_CPU_CLK].opaque = tlb_clk_setup.opaque;
/* Internal devices init */
ppc4xx_pob_init(env);
/* OBP arbitrer */
ppc4xx_opba_init(0xef600600);
+ /* Initialize timers */
+ ppc_booke_timers_init(cpu, sysclk, 0);
/* Universal interrupt controller */
- irqs = qemu_mallocz(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
+ irqs = g_malloc0(sizeof(qemu_irq) * PPCUIC_OUTPUT_NB);
irqs[PPCUIC_OUTPUT_INT] =
((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT];
irqs[PPCUIC_OUTPUT_CINT] =
*picp = pic;
/* SDRAM controller */
/* XXX 405EP has no ECC interrupt */
- ppc4xx_sdram_init(env, pic[17], 2, ram_bases, ram_sizes, do_init);
+ ppc4xx_sdram_init(env, pic[17], 2, ram_memories,
+ ram_bases, ram_sizes, do_init);
/* External bus controller */
ppc405_ebc_init(env);
/* DMA controller */
ppc405_gpio_init(0xef600700);
/* Serial ports */
if (serial_hds[0] != NULL) {
- serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_mm_init(address_space_mem, 0xef600300, 0, pic[0],
+ PPC_SERIAL_MM_BAUDBASE, serial_hds[0],
+ DEVICE_BIG_ENDIAN);
}
if (serial_hds[1] != NULL) {
- serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_mm_init(address_space_mem, 0xef600400, 0, pic[1],
+ PPC_SERIAL_MM_BAUDBASE, serial_hds[1],
+ DEVICE_BIG_ENDIAN);
}
/* OCM */
ppc405_ocm_init(env);
projects / qemu.git / blobdiff