256<<20, 128<<20, 64<<20, 32<<20, 16<<20, 8<<20, 0
};
-CPUState *ppc440ep_init(a_ram_addr *ram_size, PCIBus **pcip,
+CPUState *ppc440ep_init(ram_addr_t *ram_size, PCIBus **pcip,
const unsigned int pci_irq_nrs[4], int do_init,
const char *cpu_model)
{
- a_target_phys_addr ram_bases[PPC440EP_SDRAM_NR_BANKS];
- a_target_phys_addr ram_sizes[PPC440EP_SDRAM_NR_BANKS];
+ target_phys_addr_t ram_bases[PPC440EP_SDRAM_NR_BANKS];
+ target_phys_addr_t ram_sizes[PPC440EP_SDRAM_NR_BANKS];
CPUState *env;
qemu_irq *pic;
qemu_irq *irqs;
qemu_irq *pci_irqs;
- if (cpu_model == NULL)
- cpu_model = "405"; // XXX: should be 440EP
+ if (cpu_model == NULL) {
+ cpu_model = "440-Xilinx"; // XXX: should be 440EP
+ }
env = cpu_init(cpu_model);
if (!env) {
fprintf(stderr, "Unable to initialize CPU!\n");
if (serial_hds[0] != NULL) {
serial_mm_init(0xef600300, 0, pic[0], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[0], 1);
+ serial_hds[0], 1, 1);
}
if (serial_hds[1] != NULL) {
serial_mm_init(0xef600400, 0, pic[1], PPC_SERIAL_MM_BAUDBASE,
- serial_hds[1], 1);
+ serial_hds[1], 1, 1);
}
return env;