#include "hw.h"
#include "ppc.h"
#include "ppc4xx.h"
-#include "sysemu.h"
#include "qemu-log.h"
//#define DEBUG_MMIO
cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */
cpu_clk->opaque = env;
/* Set time-base frequency to sysclk */
- tb_clk->cb = ppc_emb_timers_init(env, sysclk);
+ tb_clk->cb = ppc_emb_timers_init(env, sysclk, PPC_INTERRUPT_PIT);
tb_clk->opaque = env;
ppc_dcr_init(env, NULL, NULL);
/* Register qemu callbacks */
- qemu_register_reset(&cpu_ppc_reset, env);
+ qemu_register_reset((QEMUResetHandler*)&cpu_reset, env);
return env;
}
ppcuic_trigger_irq(uic);
}
-static target_ulong dcr_read_uic (void *opaque, int dcrn)
+static uint32_t dcr_read_uic (void *opaque, int dcrn)
{
ppcuic_t *uic;
- target_ulong ret;
+ uint32_t ret;
uic = opaque;
dcrn -= uic->dcr_base;
return ret;
}
-static void dcr_write_uic (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_uic (void *opaque, int dcrn, uint32_t val)
{
ppcuic_t *uic;
uic = opaque;
dcrn -= uic->dcr_base;
- LOG_UIC("%s: dcr %d val " TARGET_FMT_lx "\n", __func__, dcrn, val);
+ LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val);
switch (dcrn) {
case DCR_UICSR:
uic->uicsr &= ~val;
&dcr_read_uic, &dcr_write_uic);
}
qemu_register_reset(ppcuic_reset, uic);
- ppcuic_reset(uic);
return qemu_allocate_irqs(&ppcuic_set_irq, uic, UIC_MAX_IRQ);
}
}
}
-static target_ulong dcr_read_sdram (void *opaque, int dcrn)
+static uint32_t dcr_read_sdram (void *opaque, int dcrn)
{
ppc4xx_sdram_t *sdram;
- target_ulong ret;
+ uint32_t ret;
sdram = opaque;
switch (dcrn) {
return ret;
}
-static void dcr_write_sdram (void *opaque, int dcrn, target_ulong val)
+static void dcr_write_sdram (void *opaque, int dcrn, uint32_t val)
{
ppc4xx_sdram_t *sdram;
/* We pre-initialize RAM banks */
sdram->status = 0x00000000;
sdram->cfg = 0x00800000;
- sdram_unmap_bcr(sdram);
}
void ppc4xx_sdram_init (CPUState *env, qemu_irq irq, int nbanks,
memset(sdram->ram_sizes, 0, 4 * sizeof(target_phys_addr_t));
memcpy(sdram->ram_sizes, ram_sizes,
nbanks * sizeof(target_phys_addr_t));
- sdram_reset(sdram);
qemu_register_reset(&sdram_reset, sdram);
ppc_dcr_register(env, SDRAM0_CFGADDR,
sdram, &dcr_read_sdram, &dcr_write_sdram);
unsigned int bank_size = sdram_bank_sizes[j];
if (bank_size <= size_left) {
- ram_bases[i] = qemu_ram_alloc(bank_size);
+ char name[32];
+ snprintf(name, sizeof(name), "ppc4xx.sdram%d", i);
+ ram_bases[i] = qemu_ram_alloc(NULL, name, bank_size);
ram_sizes[i] = bank_size;
size_left -= bank_size;
break;
}
ram_size -= size_left;
- if (ram_size)
+ if (size_left)
printf("Truncating memory to %d MiB to fit SDRAM controller limits.\n",
(int)(ram_size >> 20));