/*
- * Qemu PowerPC MPC8544DS board emualtion
+ * QEMU PowerPC MPC8544DS board emulation
*
* Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved.
*
* (at your option) any later version.
*/
-#include <dirent.h>
-
#include "config.h"
#include "qemu-common.h"
#include "net.h"
#include "kvm_ppc.h"
#include "device_tree.h"
#include "openpic.h"
-#include "ppce500.h"
+#include "ppc.h"
#include "loader.h"
#include "elf.h"
+#include "sysbus.h"
+#include "exec-memory.h"
+#include "host-utils.h"
#define BINARY_DEVICE_TREE_FILE "mpc8544ds.dtb"
#define UIMAGE_LOAD_BASE 0
#define RAM_SIZES_ALIGN (64UL << 20)
#define MPC8544_CCSRBAR_BASE 0xE0000000
+#define MPC8544_CCSRBAR_REGSIZE 0x00001000
+#define MPC8544_CCSRBAR_SIZE 0x00100000
#define MPC8544_MPIC_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x40000)
#define MPC8544_SERIAL0_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4500)
#define MPC8544_SERIAL1_REGS_BASE (MPC8544_CCSRBAR_BASE + 0x4600)
#define MPC8544_PCI_REGS_SIZE 0x1000
#define MPC8544_PCI_IO 0xE1000000
#define MPC8544_PCI_IOLEN 0x10000
+#define MPC8544_UTIL_BASE (MPC8544_CCSRBAR_BASE + 0xe0000)
+#define MPC8544_SPIN_BASE 0xEF000000
-#ifdef CONFIG_FDT
-static int mpc8544_copy_soc_cell(void *fdt, const char *node, const char *prop)
+struct boot_info
{
- uint32_t cell;
- int ret;
-
- ret = kvmppc_read_host_property(node, prop, &cell, sizeof(cell));
- if (ret < 0) {
- fprintf(stderr, "couldn't read host %s/%s\n", node, prop);
- goto out;
- }
-
- ret = qemu_devtree_setprop_cell(fdt, "/cpus/PowerPC,8544@0",
- prop, cell);
- if (ret < 0) {
- fprintf(stderr, "couldn't set guest /cpus/PowerPC,8544@0/%s\n", prop);
- goto out;
- }
-
-out:
- return ret;
-}
-#endif
+ uint32_t dt_base;
+ uint32_t dt_size;
+ uint32_t entry;
+};
-static int mpc8544_load_device_tree(target_phys_addr_t addr,
- uint32_t ramsize,
- target_phys_addr_t initrd_base,
- target_phys_addr_t initrd_size,
- const char *kernel_cmdline)
+static int mpc8544_load_device_tree(CPUPPCState *env,
+ target_phys_addr_t addr,
+ uint32_t ramsize,
+ target_phys_addr_t initrd_base,
+ target_phys_addr_t initrd_size,
+ const char *kernel_cmdline)
{
int ret = -1;
-#ifdef CONFIG_FDT
- uint32_t mem_reg_property[] = {0, ramsize};
+ uint32_t mem_reg_property[] = {0, cpu_to_be32(ramsize)};
char *filename;
int fdt_size;
void *fdt;
+ uint8_t hypercall[16];
+ uint32_t clock_freq = 400000000;
+ uint32_t tb_freq = 400000000;
+ int i;
+ char compatible[] = "MPC8544DS\0MPC85xxDS";
+ char model[] = "MPC8544DS";
+ char soc[128];
+ char ser0[128];
+ char ser1[128];
filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE);
if (!filename) {
goto out;
}
fdt = load_device_tree(filename, &fdt_size);
- qemu_free(filename);
+ g_free(filename);
if (fdt == NULL) {
goto out;
}
/* Manipulate device tree in memory. */
- ret = qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
- sizeof(mem_reg_property));
- if (ret < 0)
- fprintf(stderr, "couldn't set /memory/reg\n");
-
- ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
- initrd_base);
- if (ret < 0)
- fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
+ qemu_devtree_setprop_string(fdt, "/", "model", model);
+ qemu_devtree_setprop(fdt, "/", "compatible", compatible,
+ sizeof(compatible));
+ qemu_devtree_setprop_cell(fdt, "/", "#address-cells", 1);
+ qemu_devtree_setprop_cell(fdt, "/", "#size-cells", 1);
+
+ qemu_devtree_add_subnode(fdt, "/memory");
+ qemu_devtree_setprop_string(fdt, "/memory", "device_type", "memory");
+ qemu_devtree_setprop(fdt, "/memory", "reg", mem_reg_property,
+ sizeof(mem_reg_property));
+
+ qemu_devtree_add_subnode(fdt, "/chosen");
+ if (initrd_size) {
+ ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-start",
+ initrd_base);
+ if (ret < 0) {
+ fprintf(stderr, "couldn't set /chosen/linux,initrd-start\n");
+ }
- ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
- (initrd_base + initrd_size));
- if (ret < 0)
- fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
+ ret = qemu_devtree_setprop_cell(fdt, "/chosen", "linux,initrd-end",
+ (initrd_base + initrd_size));
+ if (ret < 0) {
+ fprintf(stderr, "couldn't set /chosen/linux,initrd-end\n");
+ }
+ }
ret = qemu_devtree_setprop_string(fdt, "/chosen", "bootargs",
kernel_cmdline);
fprintf(stderr, "couldn't set /chosen/bootargs\n");
if (kvm_enabled()) {
- struct dirent *dirp;
- DIR *dp;
- char buf[128];
-
- if ((dp = opendir("/proc/device-tree/cpus/")) == NULL) {
- printf("Can't open directory /proc/device-tree/cpus/\n");
- ret = -1;
- goto out;
- }
+ /* Read out host's frequencies */
+ clock_freq = kvmppc_get_clockfreq();
+ tb_freq = kvmppc_get_tbfreq();
+
+ /* indicate KVM hypercall interface */
+ qemu_devtree_add_subnode(fdt, "/hypervisor");
+ qemu_devtree_setprop_string(fdt, "/hypervisor", "compatible",
+ "linux,kvm");
+ kvmppc_get_hypercall(env, hypercall, sizeof(hypercall));
+ qemu_devtree_setprop(fdt, "/hypervisor", "hcall-instructions",
+ hypercall, sizeof(hypercall));
+ }
+
+ /* Create CPU nodes */
+ qemu_devtree_add_subnode(fdt, "/cpus");
+ qemu_devtree_setprop_cell(fdt, "/cpus", "#address-cells", 1);
+ qemu_devtree_setprop_cell(fdt, "/cpus", "#size-cells", 0);
- buf[0] = '\0';
- while ((dirp = readdir(dp)) != NULL) {
- if (strncmp(dirp->d_name, "PowerPC", 7) == 0) {
- snprintf(buf, 128, "/cpus/%s", dirp->d_name);
+ /* We need to generate the cpu nodes in reverse order, so Linux can pick
+ the first node as boot node and be happy */
+ for (i = smp_cpus - 1; i >= 0; i--) {
+ char cpu_name[128];
+ uint64_t cpu_release_addr = cpu_to_be64(MPC8544_SPIN_BASE + (i * 0x20));
+
+ for (env = first_cpu; env != NULL; env = env->next_cpu) {
+ if (env->cpu_index == i) {
break;
}
}
- closedir(dp);
- if (buf[0] == '\0') {
- printf("Unknow host!\n");
- ret = -1;
- goto out;
+
+ if (!env) {
+ continue;
}
- mpc8544_copy_soc_cell(fdt, buf, "clock-frequency");
- mpc8544_copy_soc_cell(fdt, buf, "timebase-frequency");
+ snprintf(cpu_name, sizeof(cpu_name), "/cpus/PowerPC,8544@%x", env->cpu_index);
+ qemu_devtree_add_subnode(fdt, cpu_name);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "clock-frequency", clock_freq);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "timebase-frequency", tb_freq);
+ qemu_devtree_setprop_string(fdt, cpu_name, "device_type", "cpu");
+ qemu_devtree_setprop_cell(fdt, cpu_name, "reg", env->cpu_index);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-line-size",
+ env->dcache_line_size);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-line-size",
+ env->icache_line_size);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "d-cache-size", 0x8000);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "i-cache-size", 0x8000);
+ qemu_devtree_setprop_cell(fdt, cpu_name, "bus-frequency", 0);
+ if (env->cpu_index) {
+ qemu_devtree_setprop_string(fdt, cpu_name, "status", "disabled");
+ qemu_devtree_setprop_string(fdt, cpu_name, "enable-method", "spin-table");
+ qemu_devtree_setprop(fdt, cpu_name, "cpu-release-addr",
+ &cpu_release_addr, sizeof(cpu_release_addr));
+ } else {
+ qemu_devtree_setprop_string(fdt, cpu_name, "status", "okay");
+ }
}
+ qemu_devtree_add_subnode(fdt, "/aliases");
+ /* XXX These should go into their respective devices' code */
+ snprintf(soc, sizeof(soc), "/soc8544@%x", MPC8544_CCSRBAR_BASE);
+ qemu_devtree_add_subnode(fdt, soc);
+ qemu_devtree_setprop_string(fdt, soc, "device_type", "soc");
+ qemu_devtree_setprop_string(fdt, soc, "compatible", "simple-bus");
+ qemu_devtree_setprop_cell(fdt, soc, "#address-cells", 1);
+ qemu_devtree_setprop_cell(fdt, soc, "#size-cells", 1);
+ qemu_devtree_setprop_cells(fdt, soc, "ranges", 0x0, MPC8544_CCSRBAR_BASE,
+ MPC8544_CCSRBAR_SIZE);
+ qemu_devtree_setprop_cells(fdt, soc, "reg", MPC8544_CCSRBAR_BASE,
+ MPC8544_CCSRBAR_REGSIZE);
+ /* XXX should contain a reasonable value */
+ qemu_devtree_setprop_cell(fdt, soc, "bus-frequency", 0);
+
+ /*
+ * We have to generate ser1 first, because Linux takes the first
+ * device it finds in the dt as serial output device. And we generate
+ * devices in reverse order to the dt.
+ */
+ snprintf(ser1, sizeof(ser1), "%s/serial@%x", soc,
+ MPC8544_SERIAL1_REGS_BASE - MPC8544_CCSRBAR_BASE);
+ qemu_devtree_add_subnode(fdt, ser1);
+ qemu_devtree_setprop_string(fdt, ser1, "device_type", "serial");
+ qemu_devtree_setprop_string(fdt, ser1, "compatible", "ns16550");
+ qemu_devtree_setprop_cells(fdt, ser1, "reg", MPC8544_SERIAL1_REGS_BASE -
+ MPC8544_CCSRBAR_BASE, 0x100);
+ qemu_devtree_setprop_cell(fdt, ser1, "cell-index", 1);
+ qemu_devtree_setprop_cell(fdt, ser1, "clock-frequency", 0);
+ qemu_devtree_setprop_cells(fdt, ser1, "interrupts", 42, 2);
+ qemu_devtree_setprop_phandle(fdt, ser1, "interrupt-parent", mpic);
+ qemu_devtree_setprop_string(fdt, "/aliases", "serial1", ser1);
+
+ snprintf(ser0, sizeof(ser0), "%s/serial@%x", soc,
+ MPC8544_SERIAL0_REGS_BASE - MPC8544_CCSRBAR_BASE);
+ qemu_devtree_add_subnode(fdt, ser0);
+ qemu_devtree_setprop_string(fdt, ser0, "device_type", "serial");
+ qemu_devtree_setprop_string(fdt, ser0, "compatible", "ns16550");
+ qemu_devtree_setprop_cells(fdt, ser0, "reg", MPC8544_SERIAL0_REGS_BASE -
+ MPC8544_CCSRBAR_BASE, 0x100);
+ qemu_devtree_setprop_cell(fdt, ser0, "cell-index", 0);
+ qemu_devtree_setprop_cell(fdt, ser0, "clock-frequency", 0);
+ qemu_devtree_setprop_cells(fdt, ser0, "interrupts", 42, 2);
+ qemu_devtree_setprop_phandle(fdt, ser0, "interrupt-parent", mpic);
+ qemu_devtree_setprop_string(fdt, "/aliases", "serial0", ser0);
+ qemu_devtree_setprop_string(fdt, "/chosen", "linux,stdout-path", ser0);
+
ret = rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr);
- qemu_free(fdt);
+ if (ret < 0) {
+ goto out;
+ }
+ g_free(fdt);
+ ret = fdt_size;
out:
-#endif
return ret;
}
+/* Create -kernel TLB entries for BookE. */
+static inline target_phys_addr_t booke206_page_size_to_tlb(uint64_t size)
+{
+ return 63 - clz64(size >> 10);
+}
+
+static void mmubooke_create_initial_mapping(CPUPPCState *env)
+{
+ struct boot_info *bi = env->load_info;
+ ppcmas_tlb_t *tlb = booke206_get_tlbm(env, 1, 0, 0);
+ target_phys_addr_t size, dt_end;
+ int ps;
+
+ /* Our initial TLB entry needs to cover everything from 0 to
+ the device tree top */
+ dt_end = bi->dt_base + bi->dt_size;
+ ps = booke206_page_size_to_tlb(dt_end) + 1;
+ size = (ps << MAS1_TSIZE_SHIFT);
+ tlb->mas1 = MAS1_VALID | size;
+ tlb->mas2 = 0;
+ tlb->mas7_3 = 0;
+ tlb->mas7_3 |= MAS3_UR | MAS3_UW | MAS3_UX | MAS3_SR | MAS3_SW | MAS3_SX;
+
+ env->tlb_dirty = true;
+}
+
+static void mpc8544ds_cpu_reset_sec(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+
+ cpu_reset(CPU(cpu));
+
+ /* Secondary CPU starts in halted state for now. Needs to change when
+ implementing non-kernel boot. */
+ env->halted = 1;
+ env->exception_index = EXCP_HLT;
+}
+
+static void mpc8544ds_cpu_reset(void *opaque)
+{
+ PowerPCCPU *cpu = opaque;
+ CPUPPCState *env = &cpu->env;
+ struct boot_info *bi = env->load_info;
+
+ cpu_reset(CPU(cpu));
+
+ /* Set initial guest state. */
+ env->halted = 0;
+ env->gpr[1] = (16<<20) - 8;
+ env->gpr[3] = bi->dt_base;
+ env->nip = bi->entry;
+ mmubooke_create_initial_mapping(env);
+}
+
static void mpc8544ds_init(ram_addr_t ram_size,
const char *boot_device,
const char *kernel_filename,
const char *initrd_filename,
const char *cpu_model)
{
+ MemoryRegion *address_space_mem = get_system_memory();
+ MemoryRegion *ram = g_new(MemoryRegion, 1);
PCIBus *pci_bus;
- CPUState *env;
+ CPUPPCState *env = NULL;
uint64_t elf_entry;
uint64_t elf_lowaddr;
target_phys_addr_t entry=0;
target_long initrd_size=0;
int i=0;
unsigned int pci_irq_nrs[4] = {1, 2, 3, 4};
- qemu_irq *irqs, *mpic, *pci_irqs;
+ qemu_irq **irqs, *mpic;
+ DeviceState *dev;
+ CPUPPCState *firstenv = NULL;
+
+ /* Setup CPUs */
+ if (cpu_model == NULL) {
+ cpu_model = "e500v2_v30";
+ }
+
+ irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *));
+ irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
+ for (i = 0; i < smp_cpus; i++) {
+ PowerPCCPU *cpu;
+ qemu_irq *input;
- /* Setup CPU */
- env = cpu_ppc_init("e500v2_v30");
- if (!env) {
- fprintf(stderr, "Unable to initialize CPU!\n");
- exit(1);
+ cpu = cpu_ppc_init(cpu_model);
+ if (cpu == NULL) {
+ fprintf(stderr, "Unable to initialize CPU!\n");
+ exit(1);
+ }
+ env = &cpu->env;
+
+ if (!firstenv) {
+ firstenv = env;
+ }
+
+ irqs[i] = irqs[0] + (i * OPENPIC_OUTPUT_NB);
+ input = (qemu_irq *)env->irq_inputs;
+ irqs[i][OPENPIC_OUTPUT_INT] = input[PPCE500_INPUT_INT];
+ irqs[i][OPENPIC_OUTPUT_CINT] = input[PPCE500_INPUT_CINT];
+ env->spr[SPR_BOOKE_PIR] = env->cpu_index = i;
+
+ ppc_booke_timers_init(env, 400000000, PPC_TIMER_E500);
+
+ /* Register reset handler */
+ if (!i) {
+ /* Primary CPU */
+ struct boot_info *boot_info;
+ boot_info = g_malloc0(sizeof(struct boot_info));
+ qemu_register_reset(mpc8544ds_cpu_reset, cpu);
+ env->load_info = boot_info;
+ } else {
+ /* Secondary CPUs */
+ qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu);
+ }
}
+ env = firstenv;
+
/* Fixup Memory size on a alignment boundary */
ram_size &= ~(RAM_SIZES_ALIGN - 1);
/* Register Memory */
- cpu_register_physical_memory(0, ram_size, qemu_ram_alloc(NULL,
- "mpc8544ds.ram", ram_size));
+ memory_region_init_ram(ram, "mpc8544ds.ram", ram_size);
+ vmstate_register_ram_global(ram);
+ memory_region_add_subregion(address_space_mem, 0, ram);
/* MPIC */
- irqs = qemu_mallocz(sizeof(qemu_irq) * OPENPIC_OUTPUT_NB);
- irqs[OPENPIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_INT];
- irqs[OPENPIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPCE500_INPUT_CINT];
- mpic = mpic_init(MPC8544_MPIC_REGS_BASE, 1, &irqs, NULL);
+ mpic = mpic_init(address_space_mem, MPC8544_MPIC_REGS_BASE,
+ smp_cpus, irqs, NULL);
+
+ if (!mpic) {
+ cpu_abort(env, "MPIC failed to initialize\n");
+ }
/* Serial */
if (serial_hds[0]) {
- serial_mm_init(MPC8544_SERIAL0_REGS_BASE,
+ serial_mm_init(address_space_mem, MPC8544_SERIAL0_REGS_BASE,
0, mpic[12+26], 399193,
- serial_hds[0], 1, 1);
+ serial_hds[0], DEVICE_BIG_ENDIAN);
}
if (serial_hds[1]) {
- serial_mm_init(MPC8544_SERIAL1_REGS_BASE,
+ serial_mm_init(address_space_mem, MPC8544_SERIAL1_REGS_BASE,
0, mpic[12+26], 399193,
- serial_hds[0], 1, 1);
+ serial_hds[0], DEVICE_BIG_ENDIAN);
}
+ /* General Utility device */
+ sysbus_create_simple("mpc8544-guts", MPC8544_UTIL_BASE, NULL);
+
/* PCI */
- pci_irqs = qemu_malloc(sizeof(qemu_irq) * 4);
- pci_irqs[0] = mpic[pci_irq_nrs[0]];
- pci_irqs[1] = mpic[pci_irq_nrs[1]];
- pci_irqs[2] = mpic[pci_irq_nrs[2]];
- pci_irqs[3] = mpic[pci_irq_nrs[3]];
- pci_bus = ppce500_pci_init(pci_irqs, MPC8544_PCI_REGS_BASE);
+ dev = sysbus_create_varargs("e500-pcihost", MPC8544_PCI_REGS_BASE,
+ mpic[pci_irq_nrs[0]], mpic[pci_irq_nrs[1]],
+ mpic[pci_irq_nrs[2]], mpic[pci_irq_nrs[3]],
+ NULL);
+ pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
if (!pci_bus)
printf("couldn't create PCI controller!\n");
- isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN, 1);
+ isa_mmio_init(MPC8544_PCI_IO, MPC8544_PCI_IOLEN);
if (pci_bus) {
/* Register network interfaces. */
}
}
+ /* Register spinning region */
+ sysbus_create_simple("e500-spin", MPC8544_SPIN_BASE, NULL);
+
/* Load kernel. */
if (kernel_filename) {
kernel_size = load_uimage(kernel_filename, &entry, &loadaddr, NULL);
/* If we're loading a kernel directly, we must load the device tree too. */
if (kernel_filename) {
- dt_base = (kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
- if (mpc8544_load_device_tree(dt_base, ram_size,
- initrd_base, initrd_size, kernel_cmdline) < 0) {
+ struct boot_info *boot_info;
+ int dt_size;
+
+ dt_base = (loadaddr + kernel_size + DTC_LOAD_PAD) & ~DTC_PAD_MASK;
+ dt_size = mpc8544_load_device_tree(env, dt_base, ram_size, initrd_base,
+ initrd_size, kernel_cmdline);
+ if (dt_size < 0) {
fprintf(stderr, "couldn't load device tree\n");
exit(1);
}
- cpu_synchronize_state(env);
-
- /* Set initial guest state. */
- env->gpr[1] = (16<<20) - 8;
- env->gpr[3] = dt_base;
- env->nip = entry;
- /* XXX we currently depend on KVM to create some initial TLB entries. */
+ boot_info = env->load_info;
+ boot_info->entry = entry;
+ boot_info->dt_base = dt_base;
+ boot_info->dt_size = dt_size;
}
- if (kvm_enabled())
+ if (kvm_enabled()) {
kvmppc_init();
-
- return;
+ }
}
static QEMUMachine mpc8544ds_machine = {
.name = "mpc8544ds",
.desc = "mpc8544ds",
.init = mpc8544ds_init,
+ .max_cpus = 15,
};
static void mpc8544ds_machine_init(void)
projects / qemu.git / blobdiff