static uint32_t pxa2xx_pm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->pm_base;
switch (addr) {
case PMCR ... PCMD31:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->pm_base;
switch (addr) {
case PMCR:
static uint32_t pxa2xx_cm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->cm_base;
switch (addr) {
case CCCR:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->cm_base;
switch (addr) {
case CCCR:
static uint32_t pxa2xx_mm_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->mm_base;
switch (addr) {
case MDCNFG ... SA1110:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->mm_base;
switch (addr) {
case MDCNFG ... SA1110:
/* Synchronous Serial Ports */
struct pxa2xx_ssp_s {
- target_phys_addr_t base;
qemu_irq irq;
int enable;
{
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
uint32_t retval;
- addr -= s->base;
switch (addr) {
case SSCR0:
uint32_t value)
{
struct pxa2xx_ssp_s *s = (struct pxa2xx_ssp_s *) opaque;
- addr -= s->base;
switch (addr) {
case SSCR0:
static uint32_t pxa2xx_rtc_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->rtc_base;
switch (addr) {
case RTTR:
uint32_t value)
{
struct pxa2xx_state_s *s = (struct pxa2xx_state_s *) opaque;
- addr -= s->rtc_base;
switch (addr) {
case RTTR:
static void pxa2xx_rtc_init(struct pxa2xx_state_s *s)
{
- struct tm *tm;
- time_t ti;
+ struct tm tm;
int wom;
s->rttr = 0x7fff;
s->rtsr = 0;
- time(&ti);
- if (rtc_utc)
- tm = gmtime(&ti);
- else
- tm = localtime(&ti);
- wom = ((tm->tm_mday - 1) / 7) + 1;
-
- s->last_rcnr = (uint32_t) ti;
- s->last_rdcr = (wom << 20) | ((tm->tm_wday + 1) << 17) |
- (tm->tm_hour << 12) | (tm->tm_min << 6) | tm->tm_sec;
- s->last_rycr = ((tm->tm_year + 1900) << 9) |
- ((tm->tm_mon + 1) << 5) | tm->tm_mday;
- s->last_swcr = (tm->tm_hour << 19) |
- (tm->tm_min << 13) | (tm->tm_sec << 7);
+ qemu_get_timedate(&tm, 0);
+ wom = ((tm.tm_mday - 1) / 7) + 1;
+
+ s->last_rcnr = (uint32_t) mktime(&tm);
+ s->last_rdcr = (wom << 20) | ((tm.tm_wday + 1) << 17) |
+ (tm.tm_hour << 12) | (tm.tm_min << 6) | tm.tm_sec;
+ s->last_rycr = ((tm.tm_year + 1900) << 9) |
+ ((tm.tm_mon + 1) << 5) | tm.tm_mday;
+ s->last_swcr = (tm.tm_hour << 19) |
+ (tm.tm_min << 13) | (tm.tm_sec << 7);
s->last_rtcpicr = 0;
s->last_hz = s->last_sw = s->last_pi = qemu_get_clock(rt_clock);
qemu_put_be32s(f, &s->last_rycr);
qemu_put_be32s(f, &s->last_swcr);
qemu_put_be32s(f, &s->last_rtcpicr);
- qemu_put_be64s(f, &s->last_hz);
- qemu_put_be64s(f, &s->last_sw);
- qemu_put_be64s(f, &s->last_pi);
+ qemu_put_sbe64s(f, &s->last_hz);
+ qemu_put_sbe64s(f, &s->last_sw);
+ qemu_put_sbe64s(f, &s->last_pi);
}
static int pxa2xx_rtc_load(QEMUFile *f, void *opaque, int version_id)
qemu_get_be32s(f, &s->last_rycr);
qemu_get_be32s(f, &s->last_swcr);
qemu_get_be32s(f, &s->last_rtcpicr);
- qemu_get_be64s(f, &s->last_hz);
- qemu_get_be64s(f, &s->last_sw);
- qemu_get_be64s(f, &s->last_pi);
+ qemu_get_sbe64s(f, &s->last_hz);
+ qemu_get_sbe64s(f, &s->last_sw);
+ qemu_get_sbe64s(f, &s->last_pi);
pxa2xx_rtc_alarm_update(s, s->rtsr);
struct pxa2xx_i2c_s {
i2c_slave slave;
i2c_bus *bus;
- target_phys_addr_t base;
qemu_irq irq;
uint16_t control;
static uint32_t pxa2xx_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
- addr -= s->base;
+ addr &= 0xff;
switch (addr) {
case ICR:
return s->control;
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
int ack;
- addr -= s->base;
+ addr &= 0xff;
switch (addr) {
case ICR:
s->control = value & 0xfff7;
qemu_put_8s(f, &s->ibmr);
qemu_put_8s(f, &s->data);
- i2c_bus_save(f, s->bus);
i2c_slave_save(f, &s->slave);
}
{
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *) opaque;
+ if (version_id != 1)
+ return -EINVAL;
+
qemu_get_be16s(f, &s->control);
qemu_get_be16s(f, &s->status);
qemu_get_8s(f, &s->ibmr);
qemu_get_8s(f, &s->data);
- i2c_bus_load(f, s->bus);
i2c_slave_load(f, &s->slave);
return 0;
}
qemu_irq irq, uint32_t page_size)
{
int iomemtype;
+ /* FIXME: Should the slave device really be on a separate bus? */
struct pxa2xx_i2c_s *s = (struct pxa2xx_i2c_s *)
i2c_slave_init(i2c_init_bus(), 0, sizeof(struct pxa2xx_i2c_s));
- s->base = base;
s->irq = irq;
s->slave.event = pxa2xx_i2c_event;
s->slave.recv = pxa2xx_i2c_rx;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2c_readfn,
pxa2xx_i2c_writefn, s);
- cpu_register_physical_memory(s->base & ~page_size, page_size, iomemtype);
+ cpu_register_physical_memory(base & ~page_size, page_size + 1, iomemtype);
- register_savevm("pxa2xx_i2c", base, 0,
+ register_savevm("pxa2xx_i2c", base, 1,
pxa2xx_i2c_save, pxa2xx_i2c_load, s);
return s;
static uint32_t pxa2xx_i2s_read(void *opaque, target_phys_addr_t addr)
{
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
- addr -= s->base;
switch (addr) {
case SACR0:
{
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *) opaque;
uint32_t *sample;
- addr -= s->base;
switch (addr) {
case SACR0:
struct pxa2xx_i2s_s *s = (struct pxa2xx_i2s_s *)
qemu_mallocz(sizeof(struct pxa2xx_i2s_s));
- s->base = base;
s->irq = irq;
s->dma = dma;
s->data_req = pxa2xx_i2s_data_req;
iomemtype = cpu_register_io_memory(0, pxa2xx_i2s_readfn,
pxa2xx_i2s_writefn, s);
- cpu_register_physical_memory(s->base & 0xfff00000, 0x100000, iomemtype);
+ cpu_register_physical_memory(base, 0x100000, iomemtype);
register_savevm("pxa2xx_i2s", base, 0,
pxa2xx_i2s_save, pxa2xx_i2s_load, s);
/* PXA Fast Infra-red Communications Port */
struct pxa2xx_fir_s {
- target_phys_addr_t base;
qemu_irq irq;
struct pxa2xx_dma_state_s *dma;
int enable;
{
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
uint8_t ret;
- addr -= s->base;
switch (addr) {
case ICCR0:
{
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *) opaque;
uint8_t ch;
- addr -= s->base;
switch (addr) {
case ICCR0:
struct pxa2xx_fir_s *s = (struct pxa2xx_fir_s *)
qemu_mallocz(sizeof(struct pxa2xx_fir_s));
- s->base = base;
s->irq = irq;
s->dma = dma;
s->chr = chr;
iomemtype = cpu_register_io_memory(0, pxa2xx_fir_readfn,
pxa2xx_fir_writefn, s);
- cpu_register_physical_memory(s->base, 0x1000, iomemtype);
+ cpu_register_physical_memory(base, 0x1000, iomemtype);
if (chr)
qemu_chr_add_handlers(chr, pxa2xx_fir_is_empty,
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
- s->env);
-
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
for (i = 0; pxa270_serial[i].io_base; i ++)
if (serial_hds[i])
serial_mm_init(pxa270_serial[i].io_base, 2,
- s->pic[pxa270_serial[i].irqn], serial_hds[i], 1);
+ s->pic[pxa270_serial[i].irqn], 14857000/16,
+ serial_hds[i], 1);
else
break;
if (serial_hds[i])
ssp = (struct pxa2xx_ssp_s *)
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
for (i = 0; pxa27x_ssp[i].io_base; i ++) {
+ target_phys_addr_t ssp_base;
s->ssp[i] = &ssp[i];
- ssp[i].base = pxa27x_ssp[i].io_base;
+ ssp_base = pxa27x_ssp[i].io_base;
ssp[i].irq = s->pic[pxa27x_ssp[i].irqn];
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", i, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
s->i2s = pxa2xx_i2s_init(0x40400000, s->pic[PXA2XX_PIC_I2S], s->dma);
+ s->kp = pxa27x_keypad_init(0x41500000, s->pic[PXA2XX_PIC_KEYPAD]);
+
/* GPIO1 resets the processor */
/* The handler can be overridden by board-specific code */
pxa2xx_gpio_out_set(s->gpio, 1, s->reset);
fprintf(stderr, "Unable to find CPU definition\n");
exit(1);
}
- register_savevm("cpu", 0, ARM_CPU_SAVE_VERSION, cpu_save, cpu_load,
- s->env);
-
s->reset = qemu_allocate_irqs(pxa2xx_reset, s, 1)[0];
/* SDRAM & Internal Memory Storage */
for (i = 0; pxa255_serial[i].io_base; i ++)
if (serial_hds[i])
serial_mm_init(pxa255_serial[i].io_base, 2,
- s->pic[pxa255_serial[i].irqn], serial_hds[i], 1);
+ s->pic[pxa255_serial[i].irqn], 14745600/16,
+ serial_hds[i], 1);
else
break;
if (serial_hds[i])
ssp = (struct pxa2xx_ssp_s *)
qemu_mallocz(sizeof(struct pxa2xx_ssp_s) * i);
for (i = 0; pxa255_ssp[i].io_base; i ++) {
+ target_phys_addr_t ssp_base;
s->ssp[i] = &ssp[i];
- ssp[i].base = pxa255_ssp[i].io_base;
+ ssp_base = pxa255_ssp[i].io_base;
ssp[i].irq = s->pic[pxa255_ssp[i].irqn];
iomemtype = cpu_register_io_memory(0, pxa2xx_ssp_readfn,
pxa2xx_ssp_writefn, &ssp[i]);
- cpu_register_physical_memory(ssp[i].base, 0x1000, iomemtype);
+ cpu_register_physical_memory(ssp_base, 0x1000, iomemtype);
register_savevm("pxa2xx_ssp", i, 0,
pxa2xx_ssp_save, pxa2xx_ssp_load, s);
}
projects / qemu.git / blobdiff