struct pxa2xx_dma_state_s {
pxa2xx_dma_handler_t handler;
- target_phys_addr_t base;
qemu_irq irq;
uint32_t stopintr;
uint32_t n, size;
uint32_t width;
uint32_t length;
- char buffer[32];
+ uint8_t buffer[32];
struct pxa2xx_dma_channel_s *ch;
if (s->running ++)
{
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
unsigned int channel;
- offset -= s->base;
switch (offset) {
case DRCMR64 ... DRCMR74:
{
struct pxa2xx_dma_state_s *s = (struct pxa2xx_dma_state_s *) opaque;
unsigned int channel;
- offset -= s->base;
switch (offset) {
case DRCMR64 ... DRCMR74:
if (value & DCSR_NODESCFETCH) {
/* No-descriptor-fetch mode */
- if (value & DCSR_RUN)
+ if (value & DCSR_RUN) {
+ s->chan[channel].state &= ~DCSR_STOPINTR;
pxa2xx_dma_run(s);
+ }
} else {
/* Descriptor-fetch mode */
if (value & DCSR_RUN) {
s->channels = channels;
s->chan = qemu_mallocz(sizeof(struct pxa2xx_dma_channel_s) * s->channels);
- s->base = base;
s->irq = irq;
s->handler = (pxa2xx_dma_handler_t) pxa2xx_dma_request;
s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);