* This code is licensed under the GPL.
*/
-#include "vl.h"
+#include "hw.h"
+#include "sysbus.h"
+#include "pxa.h"
#define PXA2XX_GPIO_BANKS 4
-struct pxa2xx_gpio_info_s {
- target_phys_addr_t base;
- qemu_irq *pic;
+typedef struct PXA2xxGPIOInfo PXA2xxGPIOInfo;
+struct PXA2xxGPIOInfo {
+ SysBusDevice busdev;
+ qemu_irq irq0, irq1, irqX;
int lines;
+ int ncpu;
CPUState *cpu_env;
/* XXX: GNU C vectors are more suitable */
uint32_t rising[PXA2XX_GPIO_BANKS];
uint32_t falling[PXA2XX_GPIO_BANKS];
uint32_t status[PXA2XX_GPIO_BANKS];
+ uint32_t gpsr[PXA2XX_GPIO_BANKS];
uint32_t gafr[PXA2XX_GPIO_BANKS * 2];
uint32_t prev_level[PXA2XX_GPIO_BANKS];
- struct {
- gpio_handler_t fn;
- void *opaque;
- } handler[PXA2XX_GPIO_BANKS * 32];
-
- void (*read_notify)(void *opaque);
- void *opaque;
+ qemu_irq handler[PXA2XX_GPIO_BANKS * 32];
+ qemu_irq read_notify;
};
static struct {
} pxa2xx_gpio_regs[0x200] = {
[0 ... 0x1ff] = { GPIO_NONE, 0 },
#define PXA2XX_REG(reg, a0, a1, a2, a3) \
- [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
+ [a0] = { reg, 0 }, [a1] = { reg, 1 }, [a2] = { reg, 2 }, [a3] = { reg, 3 },
PXA2XX_REG(GPLR, 0x000, 0x004, 0x008, 0x100)
PXA2XX_REG(GPSR, 0x018, 0x01c, 0x020, 0x118)
PXA2XX_REG(GAFR_U, 0x058, 0x060, 0x068, 0x070)
};
-static void pxa2xx_gpio_irq_update(struct pxa2xx_gpio_info_s *s)
+static void pxa2xx_gpio_irq_update(PXA2xxGPIOInfo *s)
{
if (s->status[0] & (1 << 0))
- qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_0]);
+ qemu_irq_raise(s->irq0);
else
- qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_0]);
+ qemu_irq_lower(s->irq0);
if (s->status[0] & (1 << 1))
- qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_1]);
+ qemu_irq_raise(s->irq1);
else
- qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_1]);
+ qemu_irq_lower(s->irq1);
if ((s->status[0] & ~3) | s->status[1] | s->status[2] | s->status[3])
- qemu_irq_raise(s->pic[PXA2XX_PIC_GPIO_X]);
+ qemu_irq_raise(s->irqX);
else
- qemu_irq_lower(s->pic[PXA2XX_PIC_GPIO_X]);
+ qemu_irq_lower(s->irqX);
}
/* Bitmap of pins used as standby and sleep wake-up sources. */
-const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
+static const int pxa2xx_gpio_wake[PXA2XX_GPIO_BANKS] = {
0x8003fe1b, 0x002001fc, 0xec080000, 0x0012007f,
};
-void pxa2xx_gpio_set(struct pxa2xx_gpio_info_s *s, int line, int level)
+static void pxa2xx_gpio_set(void *opaque, int line, int level)
{
+ PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
int bank;
uint32_t mask;
cpu_interrupt(s->cpu_env, CPU_INTERRUPT_EXITTB);
}
-static void pxa2xx_gpio_handler_update(struct pxa2xx_gpio_info_s *s) {
+static void pxa2xx_gpio_handler_update(PXA2xxGPIOInfo *s) {
uint32_t level, diff;
int i, bit, line;
for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
for (diff = s->prev_level[i] ^ level; diff; diff ^= 1 << bit) {
bit = ffs(diff) - 1;
line = bit + 32 * i;
- if (s->handler[line].fn)
- s->handler[line].fn(line, (level >> bit) & 1,
- s->handler[line].opaque);
+ qemu_set_irq(s->handler[line], (level >> bit) & 1);
}
s->prev_level[i] = level;
static uint32_t pxa2xx_gpio_read(void *opaque, target_phys_addr_t offset)
{
- struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
+ PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
uint32_t ret;
int bank;
- offset -= s->base;
if (offset >= 0x200)
return 0;
case GPDR: /* GPIO Pin-Direction registers */
return s->dir[bank];
+ case GPSR: /* GPIO Pin-Output Set registers */
+ printf("%s: Read from a write-only register " REG_FMT "\n",
+ __FUNCTION__, offset);
+ return s->gpsr[bank]; /* Return last written value. */
+
+ case GPCR: /* GPIO Pin-Output Clear registers */
+ printf("%s: Read from a write-only register " REG_FMT "\n",
+ __FUNCTION__, offset);
+ return 31337; /* Specified as unpredictable in the docs. */
+
case GRER: /* GPIO Rising-Edge Detect Enable registers */
return s->rising[bank];
case GPLR: /* GPIO Pin-Level registers */
ret = (s->olevel[bank] & s->dir[bank]) |
(s->ilevel[bank] & ~s->dir[bank]);
- if (s->read_notify)
- s->read_notify(s->opaque);
+ qemu_irq_raise(s->read_notify);
return ret;
case GEDR: /* GPIO Edge Detect Status registers */
return s->status[bank];
default:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
return 0;
static void pxa2xx_gpio_write(void *opaque,
target_phys_addr_t offset, uint32_t value)
{
- struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
+ PXA2xxGPIOInfo *s = (PXA2xxGPIOInfo *) opaque;
int bank;
- offset -= s->base;
if (offset >= 0x200)
return;
case GPSR: /* GPIO Pin-Output Set registers */
s->olevel[bank] |= value;
pxa2xx_gpio_handler_update(s);
+ s->gpsr[bank] = value;
break;
case GPCR: /* GPIO Pin-Output Clear registers */
break;
default:
- cpu_abort(cpu_single_env,
- "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
+ hw_error("%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
}
}
-static CPUReadMemoryFunc *pxa2xx_gpio_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_gpio_readfn[] = {
pxa2xx_gpio_read,
pxa2xx_gpio_read,
pxa2xx_gpio_read
};
-static CPUWriteMemoryFunc *pxa2xx_gpio_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_gpio_writefn[] = {
pxa2xx_gpio_write,
pxa2xx_gpio_write,
pxa2xx_gpio_write
};
-static void pxa2xx_gpio_save(QEMUFile *f, void *opaque)
+DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
+ CPUState *env, DeviceState *pic, int lines)
{
- struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
- int i;
-
- qemu_put_be32(f, s->lines);
-
- for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
- qemu_put_be32s(f, &s->ilevel[i]);
- qemu_put_be32s(f, &s->olevel[i]);
- qemu_put_be32s(f, &s->dir[i]);
- qemu_put_be32s(f, &s->rising[i]);
- qemu_put_be32s(f, &s->falling[i]);
- qemu_put_be32s(f, &s->status[i]);
- qemu_put_be32s(f, &s->gafr[i * 2 + 0]);
- qemu_put_be32s(f, &s->gafr[i * 2 + 1]);
-
- qemu_put_be32s(f, &s->prev_level[i]);
- }
+ DeviceState *dev;
+
+ dev = qdev_create(NULL, "pxa2xx-gpio");
+ qdev_prop_set_int32(dev, "lines", lines);
+ qdev_prop_set_int32(dev, "ncpu", env->cpu_index);
+ qdev_init_nofail(dev);
+
+ sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
+ sysbus_connect_irq(sysbus_from_qdev(dev), 0,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_0));
+ sysbus_connect_irq(sysbus_from_qdev(dev), 1,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_1));
+ sysbus_connect_irq(sysbus_from_qdev(dev), 2,
+ qdev_get_gpio_in(pic, PXA2XX_PIC_GPIO_X));
+
+ return dev;
}
-static int pxa2xx_gpio_load(QEMUFile *f, void *opaque, int version_id)
-{
- struct pxa2xx_gpio_info_s *s = (struct pxa2xx_gpio_info_s *) opaque;
- int i;
-
- if (qemu_get_be32(f) != s->lines)
- return -EINVAL;
-
- for (i = 0; i < PXA2XX_GPIO_BANKS; i ++) {
- qemu_get_be32s(f, &s->ilevel[i]);
- qemu_get_be32s(f, &s->olevel[i]);
- qemu_get_be32s(f, &s->dir[i]);
- qemu_get_be32s(f, &s->rising[i]);
- qemu_get_be32s(f, &s->falling[i]);
- qemu_get_be32s(f, &s->status[i]);
- qemu_get_be32s(f, &s->gafr[i * 2 + 0]);
- qemu_get_be32s(f, &s->gafr[i * 2 + 1]);
-
- qemu_get_be32s(f, &s->prev_level[i]);
- }
-
- return 0;
-}
-
-struct pxa2xx_gpio_info_s *pxa2xx_gpio_init(target_phys_addr_t base,
- CPUState *env, qemu_irq *pic, int lines)
+static int pxa2xx_gpio_initfn(SysBusDevice *dev)
{
int iomemtype;
- struct pxa2xx_gpio_info_s *s;
+ PXA2xxGPIOInfo *s;
- s = (struct pxa2xx_gpio_info_s *)
- qemu_mallocz(sizeof(struct pxa2xx_gpio_info_s));
- memset(s, 0, sizeof(struct pxa2xx_gpio_info_s));
- s->base = base;
- s->pic = pic;
- s->lines = lines;
- s->cpu_env = env;
+ s = FROM_SYSBUS(PXA2xxGPIOInfo, dev);
- iomemtype = cpu_register_io_memory(0, pxa2xx_gpio_readfn,
- pxa2xx_gpio_writefn, s);
- cpu_register_physical_memory(base, 0x00000fff, iomemtype);
+ s->cpu_env = qemu_get_cpu(s->ncpu);
- register_savevm("pxa2xx_gpio", 0, 0,
- pxa2xx_gpio_save, pxa2xx_gpio_load, s);
+ qdev_init_gpio_in(&dev->qdev, pxa2xx_gpio_set, s->lines);
+ qdev_init_gpio_out(&dev->qdev, s->handler, s->lines);
- return s;
-}
+ iomemtype = cpu_register_io_memory(pxa2xx_gpio_readfn,
+ pxa2xx_gpio_writefn, s, DEVICE_NATIVE_ENDIAN);
-void pxa2xx_gpio_handler_set(struct pxa2xx_gpio_info_s *s, int line,
- gpio_handler_t handler, void *opaque) {
- if (line >= s->lines) {
- printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
- return;
- }
+ sysbus_init_mmio(dev, 0x1000, iomemtype);
+ sysbus_init_irq(dev, &s->irq0);
+ sysbus_init_irq(dev, &s->irq1);
+ sysbus_init_irq(dev, &s->irqX);
- s->handler[line].fn = handler;
- s->handler[line].opaque = opaque;
+ return 0;
}
/*
* Registers a callback to notify on GPLR reads. This normally
* shouldn't be needed but it is used for the hack on Spitz machines.
*/
-void pxa2xx_gpio_read_notifier(struct pxa2xx_gpio_info_s *s,
- void (*handler)(void *opaque), void *opaque) {
+void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler)
+{
+ PXA2xxGPIOInfo *s = FROM_SYSBUS(PXA2xxGPIOInfo, sysbus_from_qdev(dev));
s->read_notify = handler;
- s->opaque = opaque;
}
+
+static const VMStateDescription vmstate_pxa2xx_gpio_regs = {
+ .name = "pxa2xx-gpio",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_INT32(lines, PXA2xxGPIOInfo),
+ VMSTATE_UINT32_ARRAY(ilevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(olevel, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(dir, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(rising, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(falling, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(status, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS),
+ VMSTATE_UINT32_ARRAY(gafr, PXA2xxGPIOInfo, PXA2XX_GPIO_BANKS * 2),
+ VMSTATE_END_OF_LIST(),
+ },
+};
+
+static SysBusDeviceInfo pxa2xx_gpio_info = {
+ .init = pxa2xx_gpio_initfn,
+ .qdev.name = "pxa2xx-gpio",
+ .qdev.desc = "PXA2xx GPIO controller",
+ .qdev.size = sizeof(PXA2xxGPIOInfo),
+ .qdev.props = (Property []) {
+ DEFINE_PROP_INT32("lines", PXA2xxGPIOInfo, lines, 0),
+ DEFINE_PROP_INT32("ncpu", PXA2xxGPIOInfo, ncpu, 0),
+ DEFINE_PROP_END_OF_LIST(),
+ }
+};
+
+static void pxa2xx_gpio_register(void)
+{
+ sysbus_register_withprop(&pxa2xx_gpio_info);
+}
+device_init(pxa2xx_gpio_register);
projects / qemu.git / blobdiff