versatile_pci: Declare as little endian

[qemu.git] / hw / pxa2xx_pic.c

diff --git a/hw/pxa2xx_pic.c b/hw/pxa2xx_pic.c
index a4d56d81611d187376ceff0b5f515396a9a04680..a36da233d391dc68dbd15a29c2024139912c66f3 100644 (file)
--- a/hw/pxa2xx_pic.c
+++ b/hw/pxa2xx_pic.c
@@ -229,13 +229,13 @@ static void pxa2xx_pic_cp_write(void *opaque, int op2, int reg, int crm,
     pxa2xx_pic_mem_write(opaque, offset, value);
 }
 
-static CPUReadMemoryFunc *pxa2xx_pic_readfn[] = {
+static CPUReadMemoryFunc * const pxa2xx_pic_readfn[] = {
     pxa2xx_pic_mem_read,
     pxa2xx_pic_mem_read,
     pxa2xx_pic_mem_read,
 };
 
-static CPUWriteMemoryFunc *pxa2xx_pic_writefn[] = {
+static CPUWriteMemoryFunc * const pxa2xx_pic_writefn[] = {
     pxa2xx_pic_mem_write,
     pxa2xx_pic_mem_write,
     pxa2xx_pic_mem_write,
@@ -300,13 +300,14 @@ qemu_irq *pxa2xx_pic_init(target_phys_addr_t base, CPUState *env)
 
     /* Enable IC memory-mapped registers access.  */
     iomemtype = cpu_register_io_memory(pxa2xx_pic_readfn,
-                    pxa2xx_pic_writefn, s);
+                    pxa2xx_pic_writefn, s, DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 
     /* Enable IC coprocessor access.  */
     cpu_arm_set_cp_io(env, 6, pxa2xx_pic_cp_read, pxa2xx_pic_cp_write, s);
 
-    register_savevm("pxa2xx_pic", 0, 0, pxa2xx_pic_save, pxa2xx_pic_load, s);
+    register_savevm(NULL, "pxa2xx_pic", 0, 0, pxa2xx_pic_save,
+                    pxa2xx_pic_load, s);
 
     return qi;
 }