#define VLAN_HLEN (ETHER_TYPE_LEN + VLAN_TCI_LEN)
#if defined (DEBUG_RTL8139)
-# define DEBUG_PRINT(x) do { printf x ; } while (0)
+# define DPRINTF(fmt, ...) \
+ do { fprintf(stderr, "RTL8139: " fmt, ## __VA_ARGS__); } while (0)
#else
-# define DEBUG_PRINT(x)
+static inline GCC_FMT_ATTR(1, 2) int DPRINTF(const char *fmt, ...)
+{
+ return 0;
+}
#endif
/* Symbolic offsets to registers. */
static void prom9346_decode_command(EEprom9346 *eeprom, uint8_t command)
{
- DEBUG_PRINT(("RTL8139: eeprom command 0x%02x\n", command));
+ DPRINTF("eeprom command 0x%02x\n", command);
switch (command & Chip9346_op_mask)
{
eeprom->eedo = 0;
eeprom->tick = 0;
eeprom->mode = Chip9346_data_read;
- DEBUG_PRINT(("RTL8139: eeprom read from address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->output));
+ DPRINTF("eeprom read from address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->output);
}
break;
eeprom->input = 0;
eeprom->tick = 0;
eeprom->mode = Chip9346_none; /* Chip9346_data_write */
- DEBUG_PRINT(("RTL8139: eeprom begin write to address 0x%02x\n",
- eeprom->address));
+ DPRINTF("eeprom begin write to address 0x%02x\n",
+ eeprom->address);
}
break;
default:
switch (command & Chip9346_op_ext_mask)
{
case Chip9346_op_write_enable:
- DEBUG_PRINT(("RTL8139: eeprom write enabled\n"));
+ DPRINTF("eeprom write enabled\n");
break;
case Chip9346_op_write_all:
- DEBUG_PRINT(("RTL8139: eeprom begin write all\n"));
+ DPRINTF("eeprom begin write all\n");
break;
case Chip9346_op_write_disable:
- DEBUG_PRINT(("RTL8139: eeprom write disabled\n"));
+ DPRINTF("eeprom write disabled\n");
break;
}
break;
++ eeprom->tick;
- DEBUG_PRINT(("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi, eeprom->eedo));
+ DPRINTF("eeprom: tick %d eedi=%d eedo=%d\n", eeprom->tick, eeprom->eedi,
+ eeprom->eedo);
switch (eeprom->mode)
{
eeprom->mode = Chip9346_read_command;
eeprom->tick = 0;
eeprom->input = 0;
- DEBUG_PRINT(("eeprom: +++ synchronized, begin command read\n"));
+ DPRINTF("eeprom: +++ synchronized, begin command read\n");
}
break;
eeprom->input = 0;
eeprom->tick = 0;
- DEBUG_PRINT(("eeprom: +++ end of read, awaiting next command\n"));
+ DPRINTF("eeprom: +++ end of read, awaiting next command\n");
#else
// original behaviour
++eeprom->address;
eeprom->output = eeprom->contents[eeprom->address];
eeprom->tick = 0;
- DEBUG_PRINT(("eeprom: +++ read next address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->output));
+ DPRINTF("eeprom: +++ read next address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->output);
#endif
}
break;
eeprom->input = (eeprom->input << 1) | (bit & 1);
if (eeprom->tick == 16)
{
- DEBUG_PRINT(("RTL8139: eeprom write to address 0x%02x data=0x%04x\n",
- eeprom->address, eeprom->input));
+ DPRINTF("eeprom write to address 0x%02x data=0x%04x\n",
+ eeprom->address, eeprom->input);
eeprom->contents[eeprom->address] = eeprom->input;
eeprom->mode = Chip9346_none; /* waiting for next command after CS cycle */
{
eeprom->contents[i] = eeprom->input;
}
- DEBUG_PRINT(("RTL8139: eeprom filled with data=0x%04x\n",
- eeprom->input));
+ DPRINTF("eeprom filled with data=0x%04x\n", eeprom->input);
eeprom->mode = Chip9346_enter_command_mode;
eeprom->tick = 0;
eeprom->eesk = eesk;
eeprom->eedi = eedi;
- DEBUG_PRINT(("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n",
- eeprom->eecs, eeprom->eesk, eeprom->eedi, eeprom->eedo));
+ DPRINTF("eeprom: +++ wires CS=%d SK=%d DI=%d DO=%d\n", eeprom->eecs,
+ eeprom->eesk, eeprom->eedi, eeprom->eedo);
if (!old_eecs && eecs)
{
eeprom->output = 0;
eeprom->mode = Chip9346_enter_command_mode;
- DEBUG_PRINT(("=== eeprom: begin access, enter command mode\n"));
+ DPRINTF("=== eeprom: begin access, enter command mode\n");
}
if (!eecs)
{
- DEBUG_PRINT(("=== eeprom: end access\n"));
+ DPRINTF("=== eeprom: end access\n");
return;
}
int isr;
isr = (s->IntrStatus & s->IntrMask) & 0xffff;
- DEBUG_PRINT(("RTL8139: Set IRQ to %d (%04x %04x)\n",
- isr ? 1 : 0, s->IntrStatus, s->IntrMask));
+ DPRINTF("Set IRQ to %d (%04x %04x)\n", isr ? 1 : 0, s->IntrStatus,
+ s->IntrMask);
qemu_set_irq(s->dev.irq[0], (isr != 0));
}
/* write packet data */
if (wrapped && !(s->RxBufferSize < 65536 && rtl8139_RxWrap(s)))
{
- DEBUG_PRINT((">>> RTL8139: rx packet wrapped in buffer at %d\n", size-wrapped));
+ DPRINTF(">>> rx packet wrapped in buffer at %d\n", size - wrapped);
if (size > wrapped)
{
static const uint8_t broadcast_macaddr[6] =
{ 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
- DEBUG_PRINT((">>> RTL8139: received len=%d\n", size));
+ DPRINTF(">>> received len=%d\n", size);
/* test if board clock is stopped */
if (!s->clock_enabled)
{
- DEBUG_PRINT(("RTL8139: stopped ==========================\n"));
+ DPRINTF("stopped ==========================\n");
return -1;
}
if (!rtl8139_receiver_enabled(s))
{
- DEBUG_PRINT(("RTL8139: receiver disabled ================\n"));
+ DPRINTF("receiver disabled ================\n");
return -1;
}
/* XXX: check this */
if (s->RxConfig & AcceptAllPhys) {
/* promiscuous: receive all */
- DEBUG_PRINT((">>> RTL8139: packet received in promiscuous mode\n"));
+ DPRINTF(">>> packet received in promiscuous mode\n");
} else {
if (!memcmp(buf, broadcast_macaddr, 6)) {
/* broadcast address */
if (!(s->RxConfig & AcceptBroadcast))
{
- DEBUG_PRINT((">>> RTL8139: broadcast packet rejected\n"));
+ DPRINTF(">>> broadcast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxBroadcast;
- DEBUG_PRINT((">>> RTL8139: broadcast packet received\n"));
+ DPRINTF(">>> broadcast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkBrd;
/* multicast */
if (!(s->RxConfig & AcceptMulticast))
{
- DEBUG_PRINT((">>> RTL8139: multicast packet rejected\n"));
+ DPRINTF(">>> multicast packet rejected\n");
/* update tally counter */
++s->tally_counters.RxERR;
if (!(s->mult[mcast_idx >> 3] & (1 << (mcast_idx & 7))))
{
- DEBUG_PRINT((">>> RTL8139: multicast address mismatch\n"));
+ DPRINTF(">>> multicast address mismatch\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxMulticast;
- DEBUG_PRINT((">>> RTL8139: multicast packet received\n"));
+ DPRINTF(">>> multicast packet received\n");
/* update tally counter */
++s->tally_counters.RxOkMul;
/* match */
if (!(s->RxConfig & AcceptMyPhys))
{
- DEBUG_PRINT((">>> RTL8139: rejecting physical address matching packet\n"));
+ DPRINTF(">>> rejecting physical address matching packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
packet_header |= RxPhysical;
- DEBUG_PRINT((">>> RTL8139: physical address matching packet received\n"));
+ DPRINTF(">>> physical address matching packet received\n");
/* update tally counter */
++s->tally_counters.RxOkPhy;
} else {
- DEBUG_PRINT((">>> RTL8139: unknown packet\n"));
+ DPRINTF(">>> unknown packet\n");
/* update tally counter */
++s->tally_counters.RxERR;
if (rtl8139_cp_receiver_enabled(s))
{
- DEBUG_PRINT(("RTL8139: in C+ Rx mode ================\n"));
+ DPRINTF("in C+ Rx mode ================\n");
/* begin C+ receiver mode */
cplus_rx_ring_desc = rtl8139_addr64(s->RxRingAddrLO, s->RxRingAddrHI);
cplus_rx_ring_desc += 16 * descriptor;
- DEBUG_PRINT(("RTL8139: +++ C+ mode reading RX descriptor %d from host memory at %08x %08x = %016" PRIx64 "\n",
- descriptor, s->RxRingAddrHI, s->RxRingAddrLO, (uint64_t)cplus_rx_ring_desc));
+ DPRINTF("+++ C+ mode reading RX descriptor %d from host memory at "
+ "%08x %08x = "TARGET_FMT_plx"\n", descriptor, s->RxRingAddrHI,
+ s->RxRingAddrLO, cplus_rx_ring_desc);
uint32_t val, rxdw0,rxdw1,rxbufLO,rxbufHI;
cpu_physical_memory_read(cplus_rx_ring_desc+12, (uint8_t *)&val, 4);
rxbufHI = le32_to_cpu(val);
- DEBUG_PRINT(("RTL8139: +++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
- descriptor,
- rxdw0, rxdw1, rxbufLO, rxbufHI));
+ DPRINTF("+++ C+ mode RX descriptor %d %08x %08x %08x %08x\n",
+ descriptor, rxdw0, rxdw1, rxbufLO, rxbufHI);
if (!(rxdw0 & CP_RX_OWN))
{
- DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d is owned by host\n", descriptor));
+ DPRINTF("C+ Rx mode : descriptor %d is owned by host\n",
+ descriptor);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
rxdw1 |= CP_RX_TAVA | le16_to_cpup((uint16_t *)
&dot1q_buf[ETHER_TYPE_LEN]);
- DEBUG_PRINT(("RTL8139: C+ Rx mode : extracted vlan tag with tci: "
- "%u\n", be16_to_cpup((uint16_t *)
- &dot1q_buf[ETHER_TYPE_LEN])));
+ DPRINTF("C+ Rx mode : extracted vlan tag with tci: ""%u\n",
+ be16_to_cpup((uint16_t *)&dot1q_buf[ETHER_TYPE_LEN]));
} else {
/* reset VLAN tag flag */
rxdw1 &= ~CP_RX_TAVA;
if (size+4 > rx_space)
{
- DEBUG_PRINT(("RTL8139: C+ Rx mode : descriptor %d size %d received %d + 4\n",
- descriptor, rx_space, size));
+ DPRINTF("C+ Rx mode : descriptor %d size %d received %d + 4\n",
+ descriptor, rx_space, size);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
++s->currCPlusRxDesc;
}
- DEBUG_PRINT(("RTL8139: done C+ Rx mode ----------------\n"));
+ DPRINTF("done C+ Rx mode ----------------\n");
}
else
{
- DEBUG_PRINT(("RTL8139: in ring Rx mode ================\n"));
+ DPRINTF("in ring Rx mode ================\n");
/* begin ring receiver mode */
int avail = MOD2(s->RxBufferSize + s->RxBufPtr - s->RxBufAddr, s->RxBufferSize);
if (avail != 0 && size + 8 >= avail)
{
- DEBUG_PRINT(("rx overflow: rx buffer length %d head 0x%04x read 0x%04x === available 0x%04x need 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8));
+ DPRINTF("rx overflow: rx buffer length %d head 0x%04x "
+ "read 0x%04x === available 0x%04x need 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr, avail, size + 8);
s->IntrStatus |= RxOverflow;
++s->RxMissed;
/* now we can signal we have received something */
- DEBUG_PRINT((" received: rx buffer length %d head 0x%04x read 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
+ DPRINTF("received: rx buffer length %d head 0x%04x read 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
s->IntrStatus |= RxOK;
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: ChipCmd write val=0x%08x\n", val));
+ DPRINTF("ChipCmd write val=0x%08x\n", val);
if (val & CmdReset)
{
- DEBUG_PRINT(("RTL8139: ChipCmd reset\n"));
+ DPRINTF("ChipCmd reset\n");
rtl8139_reset(&s->dev.qdev);
}
if (val & CmdRxEnb)
{
- DEBUG_PRINT(("RTL8139: ChipCmd enable receiver\n"));
+ DPRINTF("ChipCmd enable receiver\n");
s->currCPlusRxDesc = 0;
}
if (val & CmdTxEnb)
{
- DEBUG_PRINT(("RTL8139: ChipCmd enable transmitter\n"));
+ DPRINTF("ChipCmd enable transmitter\n");
s->currCPlusTxDesc = 0;
}
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xe3, s->bChipCmdState);
/* Deassert reset pin before next read */
if (unread != 0)
{
- DEBUG_PRINT(("RTL8139: receiver buffer data available 0x%04x\n", unread));
+ DPRINTF("receiver buffer data available 0x%04x\n", unread);
return 0;
}
- DEBUG_PRINT(("RTL8139: receiver buffer is empty\n"));
+ DPRINTF("receiver buffer is empty\n");
return 1;
}
if (rtl8139_RxBufferEmpty(s))
ret |= RxBufEmpty;
- DEBUG_PRINT(("RTL8139: ChipCmd read val=0x%04x\n", ret));
+ DPRINTF("ChipCmd read val=0x%04x\n", ret);
return ret;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139C+ command register write(w) val=0x%04x\n", val));
+ DPRINTF("C+ command register write(w) val=0x%04x\n", val);
s->cplus_enabled = 1;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff84, s->CpCmd);
s->CpCmd = val;
{
uint32_t ret = s->CpCmd;
- DEBUG_PRINT(("RTL8139C+ command register read(w) val=0x%04x\n", ret));
+ DPRINTF("C+ command register read(w) val=0x%04x\n", ret);
return ret;
}
static void rtl8139_IntrMitigate_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139C+ IntrMitigate register write(w) val=0x%04x\n", val));
+ DPRINTF("C+ IntrMitigate register write(w) val=0x%04x\n", val);
}
static uint32_t rtl8139_IntrMitigate_read(RTL8139State *s)
{
uint32_t ret = 0;
- DEBUG_PRINT(("RTL8139C+ IntrMitigate register read(w) val=0x%04x\n", ret));
+ DPRINTF("C+ IntrMitigate register read(w) val=0x%04x\n", ret);
return ret;
}
-static int rtl8139_config_writeable(RTL8139State *s)
+static int rtl8139_config_writable(RTL8139State *s)
{
if (s->Cfg9346 & Cfg9346_Unlock)
{
return 1;
}
- DEBUG_PRINT(("RTL8139: Configuration registers are write-protected\n"));
+ DPRINTF("Configuration registers are write-protected\n");
return 0;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139: BasicModeCtrl register write(w) val=0x%04x\n", val));
+ DPRINTF("BasicModeCtrl register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
uint32_t mask = 0x4cff;
- if (1 || !rtl8139_config_writeable(s))
+ if (1 || !rtl8139_config_writable(s))
{
/* Speed setting and autonegotiation enable bits are read-only */
mask |= 0x3000;
{
uint32_t ret = s->BasicModeCtrl;
- DEBUG_PRINT(("RTL8139: BasicModeCtrl register read(w) val=0x%04x\n", ret));
+ DPRINTF("BasicModeCtrl register read(w) val=0x%04x\n", ret);
return ret;
}
{
val &= 0xffff;
- DEBUG_PRINT(("RTL8139: BasicModeStatus register write(w) val=0x%04x\n", val));
+ DPRINTF("BasicModeStatus register write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xff3f, s->BasicModeStatus);
s->BasicModeStatus = val;
{
uint32_t ret = s->BasicModeStatus;
- DEBUG_PRINT(("RTL8139: BasicModeStatus register read(w) val=0x%04x\n", ret));
+ DPRINTF("BasicModeStatus register read(w) val=0x%04x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Cfg9346 write val=0x%02x\n", val));
+ DPRINTF("Cfg9346 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x31, s->Cfg9346);
uint32_t opmode = val & 0xc0;
}
}
- DEBUG_PRINT(("RTL8139: Cfg9346 read val=0x%02x\n", ret));
+ DPRINTF("Cfg9346 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config0 write val=0x%02x\n", val));
+ DPRINTF("Config0 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf8, s->Config0);
s->Config0 = val;
{
uint32_t ret = s->Config0;
- DEBUG_PRINT(("RTL8139: Config0 read val=0x%02x\n", ret));
+ DPRINTF("Config0 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config1 write val=0x%02x\n", val));
+ DPRINTF("Config1 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xC, s->Config1);
s->Config1 = val;
{
uint32_t ret = s->Config1;
- DEBUG_PRINT(("RTL8139: Config1 read val=0x%02x\n", ret));
+ DPRINTF("Config1 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config3 write val=0x%02x\n", val));
+ DPRINTF("Config3 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x8F, s->Config3);
s->Config3 = val;
{
uint32_t ret = s->Config3;
- DEBUG_PRINT(("RTL8139: Config3 read val=0x%02x\n", ret));
+ DPRINTF("Config3 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config4 write val=0x%02x\n", val));
+ DPRINTF("Config4 write val=0x%02x\n", val);
- if (!rtl8139_config_writeable(s))
+ if (!rtl8139_config_writable(s)) {
return;
+ }
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x0a, s->Config4);
s->Config4 = val;
{
uint32_t ret = s->Config4;
- DEBUG_PRINT(("RTL8139: Config4 read val=0x%02x\n", ret));
+ DPRINTF("Config4 read val=0x%02x\n", ret);
return ret;
}
{
val &= 0xff;
- DEBUG_PRINT(("RTL8139: Config5 write val=0x%02x\n", val));
+ DPRINTF("Config5 write val=0x%02x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x80, s->Config5);
s->Config5 = val;
{
uint32_t ret = s->Config5;
- DEBUG_PRINT(("RTL8139: Config5 read val=0x%02x\n", ret));
+ DPRINTF("Config5 read val=0x%02x\n", ret);
return ret;
}
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: transmitter disabled; no TxConfig write val=0x%08x\n", val));
+ DPRINTF("transmitter disabled; no TxConfig write val=0x%08x\n", val);
return;
}
- DEBUG_PRINT(("RTL8139: TxConfig write val=0x%08x\n", val));
+ DPRINTF("TxConfig write val=0x%08x\n", val);
val = SET_MASKED(val, TxVersionMask | 0x8070f80f, s->TxConfig);
static void rtl8139_TxConfig_writeb(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139C TxConfig via write(b) val=0x%02x\n", val));
+ DPRINTF("RTL8139C TxConfig via write(b) val=0x%02x\n", val);
uint32_t tc = s->TxConfig;
tc &= 0xFFFFFF00;
{
uint32_t ret = s->TxConfig;
- DEBUG_PRINT(("RTL8139: TxConfig read val=0x%04x\n", ret));
+ DPRINTF("TxConfig read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_RxConfig_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxConfig write val=0x%08x\n", val));
+ DPRINTF("RxConfig write val=0x%08x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf0fc0040, s->RxConfig);
s->RxConfig = val;
/* reset buffer size and read/write pointers */
rtl8139_reset_rxring(s, 8192 << ((s->RxConfig >> 11) & 0x3));
- DEBUG_PRINT(("RTL8139: RxConfig write reset buffer size to %d\n", s->RxBufferSize));
+ DPRINTF("RxConfig write reset buffer size to %d\n", s->RxBufferSize);
}
static uint32_t rtl8139_RxConfig_read(RTL8139State *s)
{
uint32_t ret = s->RxConfig;
- DEBUG_PRINT(("RTL8139: RxConfig read val=0x%08x\n", ret));
+ DPRINTF("RxConfig read val=0x%08x\n", ret);
return ret;
}
if (!size)
{
- DEBUG_PRINT(("RTL8139: +++ empty ethernet frame\n"));
+ DPRINTF("+++ empty ethernet frame\n");
return;
}
buf = buf2;
}
- DEBUG_PRINT(("RTL8139: +++ transmit loopback mode\n"));
+ DPRINTF("+++ transmit loopback mode\n");
rtl8139_do_receive(&s->nic->nc, buf, size, do_interrupt);
if (iov) {
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: transmitter disabled\n",
- descriptor));
+ DPRINTF("+++ cannot transmit from descriptor %d: transmitter "
+ "disabled\n", descriptor);
return 0;
}
if (s->TxStatus[descriptor] & TxHostOwns)
{
- DEBUG_PRINT(("RTL8139: +++ cannot transmit from descriptor %d: owned by host (%08x)\n",
- descriptor, s->TxStatus[descriptor]));
+ DPRINTF("+++ cannot transmit from descriptor %d: owned by host "
+ "(%08x)\n", descriptor, s->TxStatus[descriptor]);
return 0;
}
- DEBUG_PRINT(("RTL8139: +++ transmitting from descriptor %d\n", descriptor));
+ DPRINTF("+++ transmitting from descriptor %d\n", descriptor);
int txsize = s->TxStatus[descriptor] & 0x1fff;
uint8_t txbuffer[0x2000];
- DEBUG_PRINT(("RTL8139: +++ transmit reading %d bytes from host memory at 0x%08x\n",
- txsize, s->TxAddr[descriptor]));
+ DPRINTF("+++ transmit reading %d bytes from host memory at 0x%08x\n",
+ txsize, s->TxAddr[descriptor]);
cpu_physical_memory_read(s->TxAddr[descriptor], txbuffer, txsize);
rtl8139_transfer_frame(s, txbuffer, txsize, 0, NULL);
- DEBUG_PRINT(("RTL8139: +++ transmitted %d bytes from descriptor %d\n", txsize, descriptor));
+ DPRINTF("+++ transmitted %d bytes from descriptor %d\n", txsize,
+ descriptor);
/* update interrupt */
s->IntrStatus |= TxOK;
{
if (!rtl8139_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode: transmitter disabled\n"));
+ DPRINTF("+++ C+ mode: transmitter disabled\n");
return 0;
}
if (!rtl8139_cp_transmitter_enabled(s))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode: C+ transmitter disabled\n"));
+ DPRINTF("+++ C+ mode: C+ transmitter disabled\n");
return 0 ;
}
/* Normal priority ring */
cplus_tx_ring_desc += 16 * descriptor;
- DEBUG_PRINT(("RTL8139: +++ C+ mode reading TX descriptor %d from host memory at %08x0x%08x = 0x%8lx\n",
- descriptor, s->TxAddr[1], s->TxAddr[0], cplus_tx_ring_desc));
+ DPRINTF("+++ C+ mode reading TX descriptor %d from host memory at "
+ "%08x0x%08x = 0x"TARGET_FMT_plx"\n", descriptor, s->TxAddr[1],
+ s->TxAddr[0], cplus_tx_ring_desc);
uint32_t val, txdw0,txdw1,txbufLO,txbufHI;
cpu_physical_memory_read(cplus_tx_ring_desc+12, (uint8_t *)&val, 4);
txbufHI = le32_to_cpu(val);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TX descriptor %d %08x %08x %08x %08x\n",
- descriptor,
- txdw0, txdw1, txbufLO, txbufHI));
+ DPRINTF("+++ C+ mode TX descriptor %d %08x %08x %08x %08x\n", descriptor,
+ txdw0, txdw1, txbufLO, txbufHI);
/* w0 ownership flag */
#define CP_TX_OWN (1<<31)
if (!(txdw0 & CP_TX_OWN))
{
- DEBUG_PRINT(("RTL8139: C+ Tx mode : descriptor %d is owned by host\n", descriptor));
+ DPRINTF("C+ Tx mode : descriptor %d is owned by host\n", descriptor);
return 0 ;
}
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : transmitting from descriptor %d\n", descriptor));
+ DPRINTF("+++ C+ Tx mode : transmitting from descriptor %d\n", descriptor);
if (txdw0 & CP_TX_FS)
{
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is first segment descriptor\n", descriptor));
+ DPRINTF("+++ C+ Tx mode : descriptor %d is first segment "
+ "descriptor\n", descriptor);
/* reset internal buffer offset */
s->cplus_txbuffer_offset = 0;
s->cplus_txbuffer = qemu_malloc(s->cplus_txbuffer_len);
s->cplus_txbuffer_offset = 0;
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer allocated space %d\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmission buffer allocated space %d\n",
+ s->cplus_txbuffer_len);
}
while (s->cplus_txbuffer && s->cplus_txbuffer_offset + txsize >= s->cplus_txbuffer_len)
s->cplus_txbuffer_len += CP_TX_BUFFER_SIZE;
s->cplus_txbuffer = qemu_realloc(s->cplus_txbuffer, s->cplus_txbuffer_len);
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission buffer space changed to %d\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmission buffer space changed to %d\n",
+ s->cplus_txbuffer_len);
}
if (!s->cplus_txbuffer)
{
/* out of memory */
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmiter failed to reallocate %d bytes\n", s->cplus_txbuffer_len));
+ DPRINTF("+++ C+ mode transmiter failed to reallocate %d bytes\n",
+ s->cplus_txbuffer_len);
/* update tally counter */
++s->tally_counters.TxERR;
/* append more data to the packet */
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmit reading %d bytes from host memory at %016" PRIx64 " to offset %d\n",
- txsize, (uint64_t)tx_addr, s->cplus_txbuffer_offset));
+ DPRINTF("+++ C+ mode transmit reading %d bytes from host memory at "
+ TARGET_FMT_plx" to offset %d\n", txsize, tx_addr,
+ s->cplus_txbuffer_offset);
cpu_physical_memory_read(tx_addr, s->cplus_txbuffer + s->cplus_txbuffer_offset, txsize);
s->cplus_txbuffer_offset += txsize;
uint8_t dot1q_buffer_space[VLAN_HLEN];
uint16_t *dot1q_buffer;
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : descriptor %d is last segment descriptor\n", descriptor));
+ DPRINTF("+++ C+ Tx mode : descriptor %d is last segment descriptor\n",
+ descriptor);
/* can transfer fully assembled packet */
if (txdw1 & CP_TX_TAGC) {
/* the vlan tag is in BE byte order in the descriptor
* BE + le_to_cpu() + ~swap()~ = cpu */
- DEBUG_PRINT(("RTL8139: +++ C+ Tx mode : inserting vlan tag with "
- "tci: %u\n", bswap16(txdw1 & CP_TX_VLAN_TAG_MASK)));
+ DPRINTF("+++ C+ Tx mode : inserting vlan tag with ""tci: %u\n",
+ bswap16(txdw1 & CP_TX_VLAN_TAG_MASK));
dot1q_buffer = (uint16_t *) dot1q_buffer_space;
dot1q_buffer[0] = cpu_to_be16(ETH_P_8021Q);
if (txdw0 & (CP_TX_IPCS | CP_TX_UDPCS | CP_TX_TCPCS | CP_TX_LGSEN))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task checksum\n"));
+ DPRINTF("+++ C+ mode offloaded task checksum\n");
/* ip packet header */
ip_header *ip = NULL;
int proto = be16_to_cpu(*(uint16_t *)(saved_buffer + 12));
if (proto == ETH_P_IP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode has IP packet\n"));
+ DPRINTF("+++ C+ mode has IP packet\n");
/* not aligned */
eth_payload_data = saved_buffer + ETH_HLEN;
ip = (ip_header*)eth_payload_data;
if (IP_HEADER_VERSION(ip) != IP_HEADER_VERSION_4) {
- DEBUG_PRINT(("RTL8139: +++ C+ mode packet has bad IP version %d expected %d\n", IP_HEADER_VERSION(ip), IP_HEADER_VERSION_4));
+ DPRINTF("+++ C+ mode packet has bad IP version %d "
+ "expected %d\n", IP_HEADER_VERSION(ip),
+ IP_HEADER_VERSION_4);
ip = NULL;
} else {
hlen = IP_HEADER_LENGTH(ip);
{
if (txdw0 & CP_TX_IPCS)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode need IP checksum\n"));
+ DPRINTF("+++ C+ mode need IP checksum\n");
if (hlen<sizeof(ip_header) || hlen>eth_payload_len) {/* min header length */
/* bad packet header len */
{
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(ip, hlen);
- DEBUG_PRINT(("RTL8139: +++ C+ mode IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
+ DPRINTF("+++ C+ mode IP header len=%d checksum=%04x\n",
+ hlen, ip->ip_sum);
}
}
if ((txdw0 & CP_TX_LGSEN) && ip_protocol == IP_PROTO_TCP)
{
-#if defined (DEBUG_RTL8139)
int large_send_mss = (txdw0 >> 16) & CP_TC_LGSEN_MSS_MASK;
-#endif
- DEBUG_PRINT(("RTL8139: +++ C+ mode offloaded task TSO MTU=%d IP data %d frame data %d specified MSS=%d\n",
- ETH_MTU, ip_data_len, saved_size - ETH_HLEN, large_send_mss));
+
+ DPRINTF("+++ C+ mode offloaded task TSO MTU=%d IP data %d "
+ "frame data %d specified MSS=%d\n", ETH_MTU,
+ ip_data_len, saved_size - ETH_HLEN, large_send_mss);
int tcp_send_offset = 0;
int send_count = 0;
int tcp_data_len = ip_data_len - tcp_hlen;
int tcp_chunk_size = ETH_MTU - hlen - tcp_hlen;
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP data len %d TCP hlen %d TCP data len %d TCP chunk size %d\n",
- ip_data_len, tcp_hlen, tcp_data_len, tcp_chunk_size));
+ DPRINTF("+++ C+ mode TSO IP data len %d TCP hlen %d TCP "
+ "data len %d TCP chunk size %d\n", ip_data_len,
+ tcp_hlen, tcp_data_len, tcp_chunk_size);
/* note the cycle below overwrites IP header data,
but restores it from saved_ip_header before sending packet */
chunk_size = tcp_data_len - tcp_send_offset;
}
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP seqno %08x\n", be32_to_cpu(p_tcp_hdr->th_seq)));
+ DPRINTF("+++ C+ mode TSO TCP seqno %08x\n",
+ be32_to_cpu(p_tcp_hdr->th_seq));
/* add 4 TCP pseudoheader fields */
/* copy IP source and destination fields */
memcpy(data_to_checksum, saved_ip_header + 12, 8);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO calculating TCP checksum for packet with %d bytes data\n", tcp_hlen + chunk_size));
+ DPRINTF("+++ C+ mode TSO calculating TCP checksum for "
+ "packet with %d bytes data\n", tcp_hlen +
+ chunk_size);
if (tcp_send_offset)
{
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, tcp_hlen + chunk_size + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO TCP checksum %04x\n", tcp_checksum));
+ DPRINTF("+++ C+ mode TSO TCP checksum %04x\n",
+ tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
ip->ip_sum = 0;
ip->ip_sum = ip_checksum(eth_payload_data, hlen);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO IP header len=%d checksum=%04x\n", hlen, ip->ip_sum));
+ DPRINTF("+++ C+ mode TSO IP header len=%d "
+ "checksum=%04x\n", hlen, ip->ip_sum);
int tso_send_size = ETH_HLEN + hlen + tcp_hlen + chunk_size;
- DEBUG_PRINT(("RTL8139: +++ C+ mode TSO transferring packet size %d\n", tso_send_size));
+ DPRINTF("+++ C+ mode TSO transferring packet size "
+ "%d\n", tso_send_size);
rtl8139_transfer_frame(s, saved_buffer, tso_send_size,
0, (uint8_t *) dot1q_buffer);
}
else if (txdw0 & (CP_TX_TCPCS|CP_TX_UDPCS))
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode need TCP or UDP checksum\n"));
+ DPRINTF("+++ C+ mode need TCP or UDP checksum\n");
/* maximum IP header length is 60 bytes */
uint8_t saved_ip_header[60];
if ((txdw0 & CP_TX_TCPCS) && ip_protocol == IP_PROTO_TCP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode calculating TCP checksum for packet with %d bytes data\n", ip_data_len));
+ DPRINTF("+++ C+ mode calculating TCP checksum for "
+ "packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_tcpip_hdr = (ip_pseudo_header *)data_to_checksum;
p_tcpip_hdr->zeros = 0;
p_tcp_hdr->th_sum = 0;
int tcp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode TCP checksum %04x\n", tcp_checksum));
+ DPRINTF("+++ C+ mode TCP checksum %04x\n",
+ tcp_checksum);
p_tcp_hdr->th_sum = tcp_checksum;
}
else if ((txdw0 & CP_TX_UDPCS) && ip_protocol == IP_PROTO_UDP)
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode calculating UDP checksum for packet with %d bytes data\n", ip_data_len));
+ DPRINTF("+++ C+ mode calculating UDP checksum for "
+ "packet with %d bytes data\n", ip_data_len);
ip_pseudo_header *p_udpip_hdr = (ip_pseudo_header *)data_to_checksum;
p_udpip_hdr->zeros = 0;
p_udp_hdr->uh_sum = 0;
int udp_checksum = ip_checksum(data_to_checksum, ip_data_len + 12);
- DEBUG_PRINT(("RTL8139: +++ C+ mode UDP checksum %04x\n", udp_checksum));
+ DPRINTF("+++ C+ mode UDP checksum %04x\n",
+ udp_checksum);
p_udp_hdr->uh_sum = udp_checksum;
}
/* update tally counter */
++s->tally_counters.TxOk;
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmitting %d bytes packet\n", saved_size));
+ DPRINTF("+++ C+ mode transmitting %d bytes packet\n", saved_size);
rtl8139_transfer_frame(s, saved_buffer, saved_size, 1,
(uint8_t *) dot1q_buffer);
}
else
{
- DEBUG_PRINT(("RTL8139: +++ C+ mode transmission continue to next descriptor\n"));
+ DPRINTF("+++ C+ mode transmission continue to next descriptor\n");
}
return 1;
/* Mark transfer completed */
if (!txcount)
{
- DEBUG_PRINT(("RTL8139: C+ mode : transmitter queue stalled, current TxDesc = %d\n",
- s->currCPlusTxDesc));
+ DPRINTF("C+ mode : transmitter queue stalled, current TxDesc = %d\n",
+ s->currCPlusTxDesc);
}
else
{
/* Mark transfer completed */
if (!txcount)
{
- DEBUG_PRINT(("RTL8139: transmitter queue stalled, current TxDesc = %d\n", s->currTxDesc));
+ DPRINTF("transmitter queue stalled, current TxDesc = %d\n",
+ s->currTxDesc);
}
}
if (s->cplus_enabled)
{
- DEBUG_PRINT(("RTL8139C+ DTCCR write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
+ DPRINTF("RTL8139C+ DTCCR write offset=0x%x val=0x%08x "
+ "descriptor=%d\n", txRegOffset, val, descriptor);
/* handle Dump Tally Counters command */
s->TxStatus[descriptor] = val;
return;
}
- DEBUG_PRINT(("RTL8139: TxStatus write offset=0x%x val=0x%08x descriptor=%d\n", txRegOffset, val, descriptor));
+ DPRINTF("TxStatus write offset=0x%x val=0x%08x descriptor=%d\n",
+ txRegOffset, val, descriptor);
/* mask only reserved bits */
val &= ~0xff00c000; /* these bits are reset on write */
{
uint32_t ret = s->TxStatus[txRegOffset/4];
- DEBUG_PRINT(("RTL8139: TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret));
+ DPRINTF("TxStatus read offset=0x%x val=0x%08x\n", txRegOffset, ret);
return ret;
}
|((s->TxStatus[0] & TxHostOwns )?TSAD_OWN0:0) ;
- DEBUG_PRINT(("RTL8139: TSAD read val=0x%04x\n", ret));
+ DPRINTF("TSAD read val=0x%04x\n", ret);
return ret;
}
{
uint16_t ret = s->CSCR;
- DEBUG_PRINT(("RTL8139: CSCR read val=0x%04x\n", ret));
+ DPRINTF("CSCR read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_TxAddr_write(RTL8139State *s, uint32_t txAddrOffset, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val));
+ DPRINTF("TxAddr write offset=0x%x val=0x%08x\n", txAddrOffset, val);
s->TxAddr[txAddrOffset/4] = val;
}
{
uint32_t ret = s->TxAddr[txAddrOffset/4];
- DEBUG_PRINT(("RTL8139: TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret));
+ DPRINTF("TxAddr read offset=0x%x val=0x%08x\n", txAddrOffset, ret);
return ret;
}
static void rtl8139_RxBufPtr_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxBufPtr write val=0x%04x\n", val));
+ DPRINTF("RxBufPtr write val=0x%04x\n", val);
/* this value is off by 16 */
s->RxBufPtr = MOD2(val + 0x10, s->RxBufferSize);
- DEBUG_PRINT((" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
- s->RxBufferSize, s->RxBufAddr, s->RxBufPtr));
+ DPRINTF(" CAPR write: rx buffer length %d head 0x%04x read 0x%04x\n",
+ s->RxBufferSize, s->RxBufAddr, s->RxBufPtr);
}
static uint32_t rtl8139_RxBufPtr_read(RTL8139State *s)
/* this value is off by 16 */
uint32_t ret = s->RxBufPtr - 0x10;
- DEBUG_PRINT(("RTL8139: RxBufPtr read val=0x%04x\n", ret));
+ DPRINTF("RxBufPtr read val=0x%04x\n", ret);
return ret;
}
/* this value is NOT off by 16 */
uint32_t ret = s->RxBufAddr;
- DEBUG_PRINT(("RTL8139: RxBufAddr read val=0x%04x\n", ret));
+ DPRINTF("RxBufAddr read val=0x%04x\n", ret);
return ret;
}
static void rtl8139_RxBuf_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: RxBuf write val=0x%08x\n", val));
+ DPRINTF("RxBuf write val=0x%08x\n", val);
s->RxBuf = val;
{
uint32_t ret = s->RxBuf;
- DEBUG_PRINT(("RTL8139: RxBuf read val=0x%08x\n", ret));
+ DPRINTF("RxBuf read val=0x%08x\n", ret);
return ret;
}
static void rtl8139_IntrMask_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: IntrMask write(w) val=0x%04x\n", val));
+ DPRINTF("IntrMask write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0x1e00, s->IntrMask);
s->IntrMask = val;
{
uint32_t ret = s->IntrMask;
- DEBUG_PRINT(("RTL8139: IntrMask read(w) val=0x%04x\n", ret));
+ DPRINTF("IntrMask read(w) val=0x%04x\n", ret);
return ret;
}
static void rtl8139_IntrStatus_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: IntrStatus write(w) val=0x%04x\n", val));
+ DPRINTF("IntrStatus write(w) val=0x%04x\n", val);
#if 0
#else
uint16_t newStatus = s->IntrStatus & ~val;
- /* mask unwriteable bits */
+ /* mask unwritable bits */
newStatus = SET_MASKED(newStatus, 0x1e00, s->IntrStatus);
/* writing 1 to interrupt status register bit clears it */
uint32_t ret = s->IntrStatus;
- DEBUG_PRINT(("RTL8139: IntrStatus read(w) val=0x%04x\n", ret));
+ DPRINTF("IntrStatus read(w) val=0x%04x\n", ret);
#if 0
static void rtl8139_MultiIntr_write(RTL8139State *s, uint32_t val)
{
- DEBUG_PRINT(("RTL8139: MultiIntr write(w) val=0x%04x\n", val));
+ DPRINTF("MultiIntr write(w) val=0x%04x\n", val);
- /* mask unwriteable bits */
+ /* mask unwritable bits */
val = SET_MASKED(val, 0xf000, s->MultiIntr);
s->MultiIntr = val;
{
uint32_t ret = s->MultiIntr;
- DEBUG_PRINT(("RTL8139: MultiIntr read(w) val=0x%04x\n", ret));
+ DPRINTF("MultiIntr read(w) val=0x%04x\n", ret);
return ret;
}
break;
case MediaStatus:
/* ignore */
- DEBUG_PRINT(("RTL8139: not implemented write(b) to MediaStatus val=0x%02x\n", val));
+ DPRINTF("not implemented write(b) to MediaStatus val=0x%02x\n",
+ val);
break;
case HltClk:
- DEBUG_PRINT(("RTL8139: HltClk write val=0x%08x\n", val));
+ DPRINTF("HltClk write val=0x%08x\n", val);
if (val == 'R')
{
s->clock_enabled = 1;
break;
case TxThresh:
- DEBUG_PRINT(("RTL8139C+ TxThresh write(b) val=0x%02x\n", val));
+ DPRINTF("C+ TxThresh write(b) val=0x%02x\n", val);
s->TxThresh = val;
break;
case TxPoll:
- DEBUG_PRINT(("RTL8139C+ TxPoll write(b) val=0x%02x\n", val));
+ DPRINTF("C+ TxPoll write(b) val=0x%02x\n", val);
if (val & (1 << 7))
{
- DEBUG_PRINT(("RTL8139C+ TxPoll high priority transmission (not implemented)\n"));
+ DPRINTF("C+ TxPoll high priority transmission (not "
+ "implemented)\n");
//rtl8139_cplus_transmit(s);
}
if (val & (1 << 6))
{
- DEBUG_PRINT(("RTL8139C+ TxPoll normal priority transmission\n"));
+ DPRINTF("C+ TxPoll normal priority transmission\n");
rtl8139_cplus_transmit(s);
}
break;
default:
- DEBUG_PRINT(("RTL8139: not implemented write(b) addr=0x%x val=0x%02x\n", addr, val));
+ DPRINTF("not implemented write(b) addr=0x%x val=0x%02x\n", addr,
+ val);
break;
}
}
rtl8139_BasicModeStatus_write(s, val);
break;
case NWayAdvert:
- DEBUG_PRINT(("RTL8139: NWayAdvert write(w) val=0x%04x\n", val));
+ DPRINTF("NWayAdvert write(w) val=0x%04x\n", val);
s->NWayAdvert = val;
break;
case NWayLPAR:
- DEBUG_PRINT(("RTL8139: forbidden NWayLPAR write(w) val=0x%04x\n", val));
+ DPRINTF("forbidden NWayLPAR write(w) val=0x%04x\n", val);
break;
case NWayExpansion:
- DEBUG_PRINT(("RTL8139: NWayExpansion write(w) val=0x%04x\n", val));
+ DPRINTF("NWayExpansion write(w) val=0x%04x\n", val);
s->NWayExpansion = val;
break;
break;
default:
- DEBUG_PRINT(("RTL8139: ioport write(w) addr=0x%x val=0x%04x via write(b)\n", addr, val));
+ DPRINTF("ioport write(w) addr=0x%x val=0x%04x via write(b)\n",
+ addr, val);
rtl8139_io_writeb(opaque, addr, val & 0xff);
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
int64_t pci_time, next_time;
uint32_t low_pci;
- DEBUG_PRINT(("RTL8139: entered rtl8139_set_next_tctr_time\n"));
+ DPRINTF("entered rtl8139_set_next_tctr_time\n");
if (s->TimerExpire && current_time >= s->TimerExpire) {
s->IntrStatus |= PCSTimeout;
switch (addr)
{
case RxMissed:
- DEBUG_PRINT(("RTL8139: RxMissed clearing on write\n"));
+ DPRINTF("RxMissed clearing on write\n");
s->RxMissed = 0;
break;
break;
case RxRingAddrLO:
- DEBUG_PRINT(("RTL8139: C+ RxRing low bits write val=0x%08x\n", val));
+ DPRINTF("C+ RxRing low bits write val=0x%08x\n", val);
s->RxRingAddrLO = val;
break;
case RxRingAddrHI:
- DEBUG_PRINT(("RTL8139: C+ RxRing high bits write val=0x%08x\n", val));
+ DPRINTF("C+ RxRing high bits write val=0x%08x\n", val);
s->RxRingAddrHI = val;
break;
case Timer:
- DEBUG_PRINT(("RTL8139: TCTR Timer reset on write\n"));
+ DPRINTF("TCTR Timer reset on write\n");
s->TCTR_base = qemu_get_clock_ns(vm_clock);
rtl8139_set_next_tctr_time(s, s->TCTR_base);
break;
case FlashReg:
- DEBUG_PRINT(("RTL8139: FlashReg TimerInt write val=0x%08x\n", val));
+ DPRINTF("FlashReg TimerInt write val=0x%08x\n", val);
if (s->TimerInt != val) {
s->TimerInt = val;
rtl8139_set_next_tctr_time(s, qemu_get_clock_ns(vm_clock));
break;
default:
- DEBUG_PRINT(("RTL8139: ioport write(l) addr=0x%x val=0x%08x via write(b)\n", addr, val));
+ DPRINTF("ioport write(l) addr=0x%x val=0x%08x via write(b)\n",
+ addr, val);
rtl8139_io_writeb(opaque, addr, val & 0xff);
rtl8139_io_writeb(opaque, addr + 1, (val >> 8) & 0xff);
rtl8139_io_writeb(opaque, addr + 2, (val >> 16) & 0xff);
case MediaStatus:
ret = 0xd0;
- DEBUG_PRINT(("RTL8139: MediaStatus read 0x%x\n", ret));
+ DPRINTF("MediaStatus read 0x%x\n", ret);
break;
case HltClk:
ret = s->clock_enabled;
- DEBUG_PRINT(("RTL8139: HltClk read 0x%x\n", ret));
+ DPRINTF("HltClk read 0x%x\n", ret);
break;
case PCIRevisionID:
ret = RTL8139_PCI_REVID;
- DEBUG_PRINT(("RTL8139: PCI Revision ID read 0x%x\n", ret));
+ DPRINTF("PCI Revision ID read 0x%x\n", ret);
break;
case TxThresh:
ret = s->TxThresh;
- DEBUG_PRINT(("RTL8139C+ TxThresh read(b) val=0x%02x\n", ret));
+ DPRINTF("C+ TxThresh read(b) val=0x%02x\n", ret);
break;
case 0x43: /* Part of TxConfig register. Windows driver tries to read it */
ret = s->TxConfig >> 24;
- DEBUG_PRINT(("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret));
+ DPRINTF("RTL8139C TxConfig at 0x43 read(b) val=0x%02x\n", ret);
break;
default:
- DEBUG_PRINT(("RTL8139: not implemented read(b) addr=0x%x\n", addr));
+ DPRINTF("not implemented read(b) addr=0x%x\n", addr);
ret = 0;
break;
}
break;
case NWayAdvert:
ret = s->NWayAdvert;
- DEBUG_PRINT(("RTL8139: NWayAdvert read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayAdvert read(w) val=0x%04x\n", ret);
break;
case NWayLPAR:
ret = s->NWayLPAR;
- DEBUG_PRINT(("RTL8139: NWayLPAR read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayLPAR read(w) val=0x%04x\n", ret);
break;
case NWayExpansion:
ret = s->NWayExpansion;
- DEBUG_PRINT(("RTL8139: NWayExpansion read(w) val=0x%04x\n", ret));
+ DPRINTF("NWayExpansion read(w) val=0x%04x\n", ret);
break;
case CpCmd:
break;
default:
- DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x via read(b)\n", addr));
+ DPRINTF("ioport read(w) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(opaque, addr);
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
- DEBUG_PRINT(("RTL8139: ioport read(w) addr=0x%x val=0x%04x\n", addr, ret));
+ DPRINTF("ioport read(w) addr=0x%x val=0x%04x\n", addr, ret);
break;
}
case RxMissed:
ret = s->RxMissed;
- DEBUG_PRINT(("RTL8139: RxMissed read val=0x%08x\n", ret));
+ DPRINTF("RxMissed read val=0x%08x\n", ret);
break;
case TxConfig:
case RxRingAddrLO:
ret = s->RxRingAddrLO;
- DEBUG_PRINT(("RTL8139: C+ RxRing low bits read val=0x%08x\n", ret));
+ DPRINTF("C+ RxRing low bits read val=0x%08x\n", ret);
break;
case RxRingAddrHI:
ret = s->RxRingAddrHI;
- DEBUG_PRINT(("RTL8139: C+ RxRing high bits read val=0x%08x\n", ret));
+ DPRINTF("C+ RxRing high bits read val=0x%08x\n", ret);
break;
case Timer:
ret = muldiv64(qemu_get_clock_ns(vm_clock) - s->TCTR_base,
PCI_FREQUENCY, get_ticks_per_sec());
- DEBUG_PRINT(("RTL8139: TCTR Timer read val=0x%08x\n", ret));
+ DPRINTF("TCTR Timer read val=0x%08x\n", ret);
break;
case FlashReg:
ret = s->TimerInt;
- DEBUG_PRINT(("RTL8139: FlashReg TimerInt read val=0x%08x\n", ret));
+ DPRINTF("FlashReg TimerInt read val=0x%08x\n", ret);
break;
default:
- DEBUG_PRINT(("RTL8139: ioport read(l) addr=0x%x via read(b)\n", addr));
+ DPRINTF("ioport read(l) addr=0x%x via read(b)\n", addr);
ret = rtl8139_io_readb(opaque, addr);
ret |= rtl8139_io_readb(opaque, addr + 1) << 8;
ret |= rtl8139_io_readb(opaque, addr + 2) << 16;
ret |= rtl8139_io_readb(opaque, addr + 3) << 24;
- DEBUG_PRINT(("RTL8139: read(l) addr=0x%x val=%08x\n", addr, ret));
+ DPRINTF("read(l) addr=0x%x val=%08x\n", addr, ret);
break;
}
if (!s->clock_enabled)
{
- DEBUG_PRINT(("RTL8139: >>> timer: clock is not running\n"));
+ DPRINTF(">>> timer: clock is not running\n");
return;
}
uint8_t *pci_conf;
pci_conf = s->dev.config;
- pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_REALTEK);
- pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_REALTEK_8139);
- pci_conf[PCI_REVISION_ID] = RTL8139_PCI_REVID; /* >=0x20 is for 8139C+ */
- pci_config_set_class(pci_conf, PCI_CLASS_NETWORK_ETHERNET);
pci_conf[PCI_INTERRUPT_PIN] = 1; /* interrupt pin 0 */
/* TODO: start of capability list, but no capability
* list bit in status register, and offset 0xdc seems unused. */
.qdev.vmsd = &vmstate_rtl8139,
.init = pci_rtl8139_init,
.exit = pci_rtl8139_uninit,
- .romfile = "pxe-rtl8139.bin",
+ .romfile = "pxe-rtl8139.rom",
+ .vendor_id = PCI_VENDOR_ID_REALTEK,
+ .device_id = PCI_DEVICE_ID_REALTEK_8139,
+ .revision = RTL8139_PCI_REVID, /* >=0x20 is for 8139C+ */
+ .class_id = PCI_CLASS_NETWORK_ETHERNET,
.qdev.props = (Property[]) {
DEFINE_NIC_PROPERTIES(RTL8139State, conf),
DEFINE_PROP_END_OF_LIST(),
projects / qemu.git / blobdiff