Rename target_phys_addr_t to hwaddr

[qemu.git] / hw / sbi.c

diff --git a/hw/sbi.c b/hw/sbi.c
index 8d264f1aab89c7894daccb37a7b960ca39dab12c..ca78a384c7a965ba718a4d526d4a1ddde76b4bb1 100644 (file)
--- a/hw/sbi.c
+++ b/hw/sbi.c
@@ -21,17 +21,16 @@
  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  * THE SOFTWARE.
  */
-#include "hw.h"
-#include "sun4m.h"
-#include "console.h"
+
+#include "sysbus.h"
 
 //#define DEBUG_IRQ
 
 #ifdef DEBUG_IRQ
-#define DPRINTF(fmt, args...) \
-do { printf("IRQ: " fmt , ##args); } while (0)
+#define DPRINTF(fmt, ...)                                       \
+    do { printf("IRQ: " fmt , ## __VA_ARGS__); } while (0)
 #else
-#define DPRINTF(fmt, args...)
+#define DPRINTF(fmt, ...)
 #endif
 
 #define MAX_CPUS 16
@@ -39,33 +38,27 @@ do { printf("IRQ: " fmt , ##args); } while (0)
 #define SBI_NREGS 16
 
 typedef struct SBIState {
+    SysBusDevice busdev;
+    MemoryRegion iomem;
     uint32_t regs[SBI_NREGS];
     uint32_t intreg_pending[MAX_CPUS];
-    qemu_irq *cpu_irqs[MAX_CPUS];
+    qemu_irq cpu_irqs[MAX_CPUS];
     uint32_t pil_out[MAX_CPUS];
 } SBIState;
 
 #define SBI_SIZE (SBI_NREGS * 4)
-#define SBI_MASK (SBI_SIZE - 1)
-
-static void sbi_check_interrupts(void *opaque)
-{
-}
 
 static void sbi_set_irq(void *opaque, int irq, int level)
 {
 }
 
-static void sbi_set_timer_irq_cpu(void *opaque, int cpu, int level)
-{
-}
-
-static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
+static uint64_t sbi_mem_read(void *opaque, hwaddr addr,
+                             unsigned size)
 {
     SBIState *s = opaque;
     uint32_t saddr, ret;
 
-    saddr = (addr & SBI_MASK) >> 2;
+    saddr = addr >> 2;
     switch (saddr) {
     default:
         ret = s->regs[saddr];
@@ -76,13 +69,14 @@ static uint32_t sbi_mem_readl(void *opaque, target_phys_addr_t addr)
     return ret;
 }
 
-static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
+static void sbi_mem_write(void *opaque, hwaddr addr,
+                          uint64_t val, unsigned dize)
 {
     SBIState *s = opaque;
     uint32_t saddr;
 
-    saddr = (addr & SBI_MASK) >> 2;
-    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
+    saddr = addr >> 2;
+    DPRINTF("write system reg 0x" TARGET_FMT_plx " = %x\n", addr, (int)val);
     switch (saddr) {
     default:
         s->regs[saddr] = val;
@@ -90,78 +84,73 @@ static void sbi_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
     }
 }
 
-static CPUReadMemoryFunc *sbi_mem_read[3] = {
-    NULL,
-    NULL,
-    sbi_mem_readl,
+static const MemoryRegionOps sbi_mem_ops = {
+    .read = sbi_mem_read,
+    .write = sbi_mem_write,
+    .endianness = DEVICE_NATIVE_ENDIAN,
+    .valid = {
+        .min_access_size = 4,
+        .max_access_size = 4,
+    },
 };
 
-static CPUWriteMemoryFunc *sbi_mem_write[3] = {
-    NULL,
-    NULL,
-    sbi_mem_writel,
+static const VMStateDescription vmstate_sbi = {
+    .name ="sbi",
+    .version_id = 1,
+    .minimum_version_id = 1,
+    .minimum_version_id_old = 1,
+    .fields      = (VMStateField []) {
+        VMSTATE_UINT32_ARRAY(intreg_pending, SBIState, MAX_CPUS),
+        VMSTATE_END_OF_LIST()
+    }
 };
 
-static void sbi_save(QEMUFile *f, void *opaque)
+static void sbi_reset(DeviceState *d)
 {
-    SBIState *s = opaque;
+    SBIState *s = container_of(d, SBIState, busdev.qdev);
     unsigned int i;
 
     for (i = 0; i < MAX_CPUS; i++) {
-        qemu_put_be32s(f, &s->intreg_pending[i]);
+        s->intreg_pending[i] = 0;
     }
 }
 
-static int sbi_load(QEMUFile *f, void *opaque, int version_id)
+static int sbi_init1(SysBusDevice *dev)
 {
-    SBIState *s = opaque;
+    SBIState *s = FROM_SYSBUS(SBIState, dev);
     unsigned int i;
 
-    if (version_id != 1)
-        return -EINVAL;
-
+    qdev_init_gpio_in(&dev->qdev, sbi_set_irq, 32 + MAX_CPUS);
     for (i = 0; i < MAX_CPUS; i++) {
-        qemu_get_be32s(f, &s->intreg_pending[i]);
+        sysbus_init_irq(dev, &s->cpu_irqs[i]);
     }
-    sbi_check_interrupts(s);
+
+    memory_region_init_io(&s->iomem, &sbi_mem_ops, s, "sbi", SBI_SIZE);
+    sysbus_init_mmio(dev, &s->iomem);
 
     return 0;
 }
 
-static void sbi_reset(void *opaque)
+static void sbi_class_init(ObjectClass *klass, void *data)
 {
-    SBIState *s = opaque;
-    unsigned int i;
+    DeviceClass *dc = DEVICE_CLASS(klass);
+    SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 
-    for (i = 0; i < MAX_CPUS; i++) {
-        s->intreg_pending[i] = 0;
-    }
-    sbi_check_interrupts(s);
+    k->init = sbi_init1;
+    dc->reset = sbi_reset;
+    dc->vmsd = &vmstate_sbi;
 }
 
-void *sbi_init(target_phys_addr_t addr, qemu_irq **irq, qemu_irq **cpu_irq,
-               qemu_irq **parent_irq)
-{
-    unsigned int i;
-    int sbi_io_memory;
-    SBIState *s;
-
-    s = qemu_mallocz(sizeof(SBIState));
-    if (!s)
-        return NULL;
-
-    for (i = 0; i < MAX_CPUS; i++) {
-        s->cpu_irqs[i] = parent_irq[i];
-    }
-
-    sbi_io_memory = cpu_register_io_memory(0, sbi_mem_read, sbi_mem_write, s);
-    cpu_register_physical_memory(addr, SBI_SIZE, sbi_io_memory);
-
-    register_savevm("sbi", addr, 1, sbi_save, sbi_load, s);
-    qemu_register_reset(sbi_reset, s);
-    *irq = qemu_allocate_irqs(sbi_set_irq, s, 32);
-    *cpu_irq = qemu_allocate_irqs(sbi_set_timer_irq_cpu, s, MAX_CPUS);
-    sbi_reset(s);
+static TypeInfo sbi_info = {
+    .name          = "sbi",
+    .parent        = TYPE_SYS_BUS_DEVICE,
+    .instance_size = sizeof(SBIState),
+    .class_init    = sbi_class_init,
+};
 
-    return s;
+static void sbi_register_types(void)
+{
+    type_register_static(&sbi_info);
 }
+
+type_init(sbi_register_types)