* Based on arm_timer.c by Paul Brook
* Copyright (c) 2005-2006 CodeSourcery.
*
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
*/
#include "hw.h"
if (s->feat & TIMER_FEAT_CAPT)
return s->tcpr;
default:
- cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
return 0;
}
}
case 4: freq >>= 10; break;
case 6:
case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TPSC value\n"); break;
+ default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
}
switch ((value & TIMER_TCR_CKEG) >> 3) {
case 0: break;
case 1:
case 2:
case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved CKEG value\n"); break;
+ default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
}
switch ((value & TIMER_TCR_ICPE) >> 6) {
case 0: break;
case 2:
case 3: if (s->feat & TIMER_FEAT_CAPT) break;
- default: cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPE value\n"); break;
+ default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
}
if ((value & TIMER_TCR_UNF) == 0)
s->int_level = 0;
value &= ~TIMER_TCR_UNF;
if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved ICPF value\n");
+ hw_error("sh_timer_write: Reserved ICPF value\n");
value &= ~TIMER_TCR_ICPF; /* capture not supported */
if (value & TIMER_TCR_RESERVED)
- cpu_abort (cpu_single_env,
- "sh_timer_write: Reserved TCR bits set\n");
+ hw_error("sh_timer_write: Reserved TCR bits set\n");
s->tcr = value;
ptimer_set_limit(s->timer, s->tcor, 0);
ptimer_set_freq(s->timer, freq);
break;
}
default:
- cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
- (int)offset);
+ hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
}
sh_timer_update(s);
}
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
return sh_timer_read(s->timer[2], offset - 0x20);
}
if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
return s->tocr;
- cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad offset %x\n", (int)offset);
return 0;
}
if (offset >= 0x20) {
if (!(s->feat & TMU012_FEAT_3CHAN))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
- (int)offset);
+ hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
sh_timer_write(s->timer[2], offset - 0x20, value);
return;
}
sh_timer_start_stop(s->timer[2], value & (1 << 2));
else
if (value & (1 << 2))
- cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
+ hw_error("tmu012_write: Bad channel\n");
s->tstr = value;
return;
}
}
-static CPUReadMemoryFunc *tmu012_readfn[] = {
+static CPUReadMemoryFunc * const tmu012_readfn[] = {
tmu012_read,
tmu012_read,
tmu012_read
};
-static CPUWriteMemoryFunc *tmu012_writefn[] = {
+static CPUWriteMemoryFunc * const tmu012_writefn[] = {
tmu012_write,
tmu012_write,
tmu012_write
if (feat & TMU012_FEAT_3CHAN)
s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
ch2_irq0); /* ch2_irq1 not supported */
- iomemtype = cpu_register_io_memory(0, tmu012_readfn,
- tmu012_writefn, s);
+ iomemtype = cpu_register_io_memory(tmu012_readfn,
+ tmu012_writefn, s,
+ DEVICE_NATIVE_ENDIAN);
cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
/* ??? Save/restore. */