Use glib memory allocation and free functions

[qemu.git] / hw / sh_timer.c

diff --git a/hw/sh_timer.c b/hw/sh_timer.c
index c5c45f50d2e511986bf7887277dfd73b71d6c225..dca3c94210b76c2f3144dfb76578cb14a4705feb 100644 (file)
--- a/hw/sh_timer.c
+++ b/hw/sh_timer.c
@@ -5,7 +5,7 @@
  * Based on arm_timer.c by Paul Brook
  * Copyright (c) 2005-2006 CodeSourcery.
  *
- * This code is licenced under the GPL.
+ * This code is licensed under the GPL.
  */
 
 #include "hw.h"
@@ -25,6 +25,11 @@
 #define TIMER_FEAT_CAPT   (1 << 0)
 #define TIMER_FEAT_EXTCLK (1 << 1)
 
+#define OFFSET_TCOR   0
+#define OFFSET_TCNT   1
+#define OFFSET_TCR    2
+#define OFFSET_TCPR   3
+
 typedef struct {
     ptimer_state *timer;
     uint32_t tcnt;
@@ -57,18 +62,17 @@ static uint32_t sh_timer_read(void *opaque, target_phys_addr_t offset)
     sh_timer_state *s = (sh_timer_state *)opaque;
 
     switch (offset >> 2) {
-    case 0:
+    case OFFSET_TCOR:
         return s->tcor;
-    case 1:
+    case OFFSET_TCNT:
         return ptimer_get_count(s->timer);
-    case 2:
+    case OFFSET_TCR:
         return s->tcr | (s->int_level ? TIMER_TCR_UNF : 0);
-    case 3:
+    case OFFSET_TCPR:
         if (s->feat & TIMER_FEAT_CAPT)
             return s->tcpr;
     default:
-        cpu_abort (cpu_single_env, "sh_timer_read: Bad offset %x\n",
-                   (int)offset);
+        hw_error("sh_timer_read: Bad offset %x\n", (int)offset);
         return 0;
     }
 }
@@ -80,15 +84,15 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
     int freq;
 
     switch (offset >> 2) {
-    case 0:
+    case OFFSET_TCOR:
         s->tcor = value;
         ptimer_set_limit(s->timer, s->tcor, 0);
         break;
-    case 1:
+    case OFFSET_TCNT:
         s->tcnt = value;
         ptimer_set_count(s->timer, s->tcnt);
         break;
-    case 2:
+    case OFFSET_TCR:
         if (s->enabled) {
             /* Pause the timer if it is running.  This may cause some
                inaccuracy dure to rounding, but avoids a whole lot of other
@@ -105,23 +109,20 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
         case 4: freq >>= 10; break;
        case 6:
        case 7: if (s->feat & TIMER_FEAT_EXTCLK) break;
-       default: cpu_abort (cpu_single_env,
-                          "sh_timer_write: Reserved TPSC value\n"); break;
+       default: hw_error("sh_timer_write: Reserved TPSC value\n"); break;
         }
         switch ((value & TIMER_TCR_CKEG) >> 3) {
        case 0: break;
         case 1:
         case 2:
         case 3: if (s->feat & TIMER_FEAT_EXTCLK) break;
-       default: cpu_abort (cpu_single_env,
-                          "sh_timer_write: Reserved CKEG value\n"); break;
+       default: hw_error("sh_timer_write: Reserved CKEG value\n"); break;
         }
         switch ((value & TIMER_TCR_ICPE) >> 6) {
        case 0: break;
         case 2:
         case 3: if (s->feat & TIMER_FEAT_CAPT) break;
-       default: cpu_abort (cpu_single_env,
-                          "sh_timer_write: Reserved ICPE value\n"); break;
+       default: hw_error("sh_timer_write: Reserved ICPE value\n"); break;
         }
        if ((value & TIMER_TCR_UNF) == 0)
             s->int_level = 0;
@@ -129,14 +130,12 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
        value &= ~TIMER_TCR_UNF;
 
        if ((value & TIMER_TCR_ICPF) && (!(s->feat & TIMER_FEAT_CAPT)))
-            cpu_abort (cpu_single_env,
-                      "sh_timer_write: Reserved ICPF value\n");
+            hw_error("sh_timer_write: Reserved ICPF value\n");
 
        value &= ~TIMER_TCR_ICPF; /* capture not supported */
 
        if (value & TIMER_TCR_RESERVED)
-            cpu_abort (cpu_single_env,
-                      "sh_timer_write: Reserved TCR bits set\n");
+            hw_error("sh_timer_write: Reserved TCR bits set\n");
         s->tcr = value;
         ptimer_set_limit(s->timer, s->tcor, 0);
         ptimer_set_freq(s->timer, freq);
@@ -145,14 +144,13 @@ static void sh_timer_write(void *opaque, target_phys_addr_t offset,
             ptimer_run(s->timer, 0);
         }
         break;
-    case 3:
+    case OFFSET_TCPR:
         if (s->feat & TIMER_FEAT_CAPT) {
             s->tcpr = value;
            break;
        }
     default:
-        cpu_abort (cpu_single_env, "sh_timer_write: Bad offset %x\n",
-                   (int)offset);
+        hw_error("sh_timer_write: Bad offset %x\n", (int)offset);
     }
     sh_timer_update(s);
 }
@@ -190,18 +188,23 @@ static void *sh_timer_init(uint32_t freq, int feat, qemu_irq irq)
     sh_timer_state *s;
     QEMUBH *bh;
 
-    s = (sh_timer_state *)qemu_mallocz(sizeof(sh_timer_state));
+    s = (sh_timer_state *)g_malloc0(sizeof(sh_timer_state));
     s->freq = freq;
     s->feat = feat;
     s->tcor = 0xffffffff;
     s->tcnt = 0xffffffff;
     s->tcpr = 0xdeadbeef;
-    s->tcor = 0;
+    s->tcr = 0;
     s->enabled = 0;
     s->irq = irq;
 
     bh = qemu_bh_new(sh_timer_tick, s);
     s->timer = ptimer_init(bh);
+
+    sh_timer_write(s, OFFSET_TCOR >> 2, s->tcor);
+    sh_timer_write(s, OFFSET_TCNT >> 2, s->tcnt);
+    sh_timer_write(s, OFFSET_TCPR >> 2, s->tcpr);
+    sh_timer_write(s, OFFSET_TCR  >> 2, s->tcpr);
     /* ??? Save/restore.  */
     return s;
 }
@@ -224,8 +227,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
 
     if (offset >= 0x20) {
         if (!(s->feat & TMU012_FEAT_3CHAN))
-           cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
-                      (int)offset);
+           hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
         return sh_timer_read(s->timer[2], offset - 0x20);
     }
 
@@ -241,8 +243,7 @@ static uint32_t tmu012_read(void *opaque, target_phys_addr_t offset)
     if ((s->feat & TMU012_FEAT_TOCR) && offset == 0)
         return s->tocr;
 
-    cpu_abort (cpu_single_env, "tmu012_write: Bad offset %x\n",
-              (int)offset);
+    hw_error("tmu012_write: Bad offset %x\n", (int)offset);
     return 0;
 }
 
@@ -257,8 +258,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
 
     if (offset >= 0x20) {
         if (!(s->feat & TMU012_FEAT_3CHAN))
-           cpu_abort (cpu_single_env, "tmu012_write: Bad channel offset %x\n",
-                      (int)offset);
+           hw_error("tmu012_write: Bad channel offset %x\n", (int)offset);
         sh_timer_write(s->timer[2], offset - 0x20, value);
        return;
     }
@@ -280,7 +280,7 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
             sh_timer_start_stop(s->timer[2], value & (1 << 2));
        else
             if (value & (1 << 2))
-                cpu_abort (cpu_single_env, "tmu012_write: Bad channel\n");
+                hw_error("tmu012_write: Bad channel\n");
 
        s->tstr = value;
        return;
@@ -291,13 +291,13 @@ static void tmu012_write(void *opaque, target_phys_addr_t offset,
     }
 }
 
-static CPUReadMemoryFunc *tmu012_readfn[] = {
+static CPUReadMemoryFunc * const tmu012_readfn[] = {
     tmu012_read,
     tmu012_read,
     tmu012_read
 };
 
-static CPUWriteMemoryFunc *tmu012_writefn[] = {
+static CPUWriteMemoryFunc * const tmu012_writefn[] = {
     tmu012_write,
     tmu012_write,
     tmu012_write
@@ -311,15 +311,16 @@ void tmu012_init(target_phys_addr_t base, int feat, uint32_t freq,
     tmu012_state *s;
     int timer_feat = (feat & TMU012_FEAT_EXTCLK) ? TIMER_FEAT_EXTCLK : 0;
 
-    s = (tmu012_state *)qemu_mallocz(sizeof(tmu012_state));
+    s = (tmu012_state *)g_malloc0(sizeof(tmu012_state));
     s->feat = feat;
     s->timer[0] = sh_timer_init(freq, timer_feat, ch0_irq);
     s->timer[1] = sh_timer_init(freq, timer_feat, ch1_irq);
     if (feat & TMU012_FEAT_3CHAN)
         s->timer[2] = sh_timer_init(freq, timer_feat | TIMER_FEAT_CAPT,
                                    ch2_irq0); /* ch2_irq1 not supported */
-    iomemtype = cpu_register_io_memory(0, tmu012_readfn,
-                                       tmu012_writefn, s);
+    iomemtype = cpu_register_io_memory(tmu012_readfn,
+                                       tmu012_writefn, s,
+                                       DEVICE_NATIVE_ENDIAN);
     cpu_register_physical_memory(P4ADDR(base), 0x00001000, iomemtype);
     cpu_register_physical_memory(A7ADDR(base), 0x00001000, iomemtype);
     /* ??? Save/restore.  */