* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
* THE SOFTWARE.
*/
-#include "hw.h"
-#include "sun4m.h"
-#include "sysemu.h"
-/* debug misc */
-//#define DEBUG_MISC
+#include "sysemu.h"
+#include "sysbus.h"
+#include "trace.h"
/*
* This is the auxio port, chip control and system control part of
* This also includes the PMC CPU idle controller.
*/
-#ifdef DEBUG_MISC
-#define MISC_DPRINTF(fmt, args...) \
-do { printf("MISC: " fmt , ##args); } while (0)
-#else
-#define MISC_DPRINTF(fmt, args...)
-#endif
-
typedef struct MiscState {
+ SysBusDevice busdev;
qemu_irq irq;
+ uint32_t dummy;
uint8_t config;
uint8_t aux1, aux2;
uint8_t diag, mctrl;
- uint32_t sysctrl;
+ uint8_t sysctrl;
uint16_t leds;
+ qemu_irq fdc_tc;
} MiscState;
+typedef struct APCState {
+ SysBusDevice busdev;
+ qemu_irq cpu_halt;
+} APCState;
+
#define MISC_SIZE 1
-#define SYSCTRL_MAXADDR 3
-#define SYSCTRL_SIZE (SYSCTRL_MAXADDR + 1)
-#define LED_MAXADDR 2
-#define LED_SIZE (LED_MAXADDR + 1)
+#define SYSCTRL_SIZE 4
+
+#define AUX1_TC 0x02
+
+#define AUX2_PWROFF 0x01
+#define AUX2_PWRINTCLR 0x02
+#define AUX2_PWRFAIL 0x20
+
+#define CFG_PWRINTEN 0x08
+
+#define SYS_RESET 0x01
+#define SYS_RESETSTAT 0x02
static void slavio_misc_update_irq(void *opaque)
{
MiscState *s = opaque;
- if ((s->aux2 & 0x4) && (s->config & 0x8)) {
- MISC_DPRINTF("Raise IRQ\n");
+ if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
+ trace_slavio_misc_update_irq_raise();
qemu_irq_raise(s->irq);
} else {
- MISC_DPRINTF("Lower IRQ\n");
+ trace_slavio_misc_update_irq_lower();
qemu_irq_lower(s->irq);
}
}
-static void slavio_misc_reset(void *opaque)
+static void slavio_misc_reset(DeviceState *d)
{
- MiscState *s = opaque;
+ MiscState *s = container_of(d, MiscState, busdev.qdev);
// Diagnostic and system control registers not cleared in reset
s->config = s->aux1 = s->aux2 = s->mctrl = 0;
}
-void slavio_set_power_fail(void *opaque, int power_failing)
+static void slavio_set_power_fail(void *opaque, int irq, int power_failing)
{
MiscState *s = opaque;
- MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
- if (power_failing && (s->config & 0x8)) {
- s->aux2 |= 0x4;
+ trace_slavio_set_power_fail(power_failing, s->config);
+ if (power_failing && (s->config & CFG_PWRINTEN)) {
+ s->aux2 |= AUX2_PWRFAIL;
} else {
- s->aux2 &= ~0x4;
+ s->aux2 &= ~AUX2_PWRFAIL;
}
slavio_misc_update_irq(s);
}
-static void slavio_misc_mem_writeb(void *opaque, target_phys_addr_t addr,
+static void slavio_cfg_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MiscState *s = opaque;
+
+ trace_slavio_cfg_mem_writeb(val & 0xff);
+ s->config = val & 0xff;
+ slavio_misc_update_irq(s);
+}
+
+static uint32_t slavio_cfg_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->config;
+ trace_slavio_cfg_mem_readb(ret);
+ return ret;
+}
+
+static CPUReadMemoryFunc * const slavio_cfg_mem_read[3] = {
+ slavio_cfg_mem_readb,
+ NULL,
+ NULL,
+};
+
+static CPUWriteMemoryFunc * const slavio_cfg_mem_write[3] = {
+ slavio_cfg_mem_writeb,
+ NULL,
+ NULL,
+};
+
+static void slavio_diag_mem_writeb(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MiscState *s = opaque;
- switch (addr & 0xfff0000) {
- case 0x1800000:
- MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
- s->config = val & 0xff;
- slavio_misc_update_irq(s);
- break;
- case 0x1900000:
- MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
- s->aux1 = val & 0xff;
- break;
- case 0x1910000:
- val &= 0x3;
- MISC_DPRINTF("Write aux2 %2.2x\n", val);
- val |= s->aux2 & 0x4;
- if (val & 0x2) // Clear Power Fail int
- val &= 0x1;
- s->aux2 = val;
- if (val & 1)
- qemu_system_shutdown_request();
- slavio_misc_update_irq(s);
- break;
- case 0x1a00000:
- MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
- s->diag = val & 0xff;
- break;
- case 0x1b00000:
- MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
- s->mctrl = val & 0xff;
- break;
- case 0xa000000:
- MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
- cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
- break;
- }
+ trace_slavio_diag_mem_writeb(val & 0xff);
+ s->diag = val & 0xff;
}
-static uint32_t slavio_misc_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint32_t slavio_diag_mem_readb(void *opaque, target_phys_addr_t addr)
{
MiscState *s = opaque;
uint32_t ret = 0;
- switch (addr & 0xfff0000) {
- case 0x1800000:
- ret = s->config;
- MISC_DPRINTF("Read config %2.2x\n", ret);
- break;
- case 0x1900000:
- ret = s->aux1;
- MISC_DPRINTF("Read aux1 %2.2x\n", ret);
- break;
- case 0x1910000:
- ret = s->aux2;
- MISC_DPRINTF("Read aux2 %2.2x\n", ret);
- break;
- case 0x1a00000:
- ret = s->diag;
- MISC_DPRINTF("Read diag %2.2x\n", ret);
- break;
- case 0x1b00000:
- ret = s->mctrl;
- MISC_DPRINTF("Read modem control %2.2x\n", ret);
- break;
- case 0xa000000:
- MISC_DPRINTF("Read power management %2.2x\n", ret);
- break;
+ ret = s->diag;
+ trace_slavio_diag_mem_readb(ret);
+ return ret;
+}
+
+static CPUReadMemoryFunc * const slavio_diag_mem_read[3] = {
+ slavio_diag_mem_readb,
+ NULL,
+ NULL,
+};
+
+static CPUWriteMemoryFunc * const slavio_diag_mem_write[3] = {
+ slavio_diag_mem_writeb,
+ NULL,
+ NULL,
+};
+
+static void slavio_mdm_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MiscState *s = opaque;
+
+ trace_slavio_mdm_mem_writeb(val & 0xff);
+ s->mctrl = val & 0xff;
+}
+
+static uint32_t slavio_mdm_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->mctrl;
+ trace_slavio_mdm_mem_readb(ret);
+ return ret;
+}
+
+static CPUReadMemoryFunc * const slavio_mdm_mem_read[3] = {
+ slavio_mdm_mem_readb,
+ NULL,
+ NULL,
+};
+
+static CPUWriteMemoryFunc * const slavio_mdm_mem_write[3] = {
+ slavio_mdm_mem_writeb,
+ NULL,
+ NULL,
+};
+
+static void slavio_aux1_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MiscState *s = opaque;
+
+ trace_slavio_aux1_mem_writeb(val & 0xff);
+ if (val & AUX1_TC) {
+ // Send a pulse to floppy terminal count line
+ if (s->fdc_tc) {
+ qemu_irq_raise(s->fdc_tc);
+ qemu_irq_lower(s->fdc_tc);
+ }
+ val &= ~AUX1_TC;
}
+ s->aux1 = val & 0xff;
+}
+
+static uint32_t slavio_aux1_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->aux1;
+ trace_slavio_aux1_mem_readb(ret);
return ret;
}
-static CPUReadMemoryFunc *slavio_misc_mem_read[3] = {
- slavio_misc_mem_readb,
- slavio_misc_mem_readb,
- slavio_misc_mem_readb,
+static CPUReadMemoryFunc * const slavio_aux1_mem_read[3] = {
+ slavio_aux1_mem_readb,
+ NULL,
+ NULL,
};
-static CPUWriteMemoryFunc *slavio_misc_mem_write[3] = {
- slavio_misc_mem_writeb,
- slavio_misc_mem_writeb,
- slavio_misc_mem_writeb,
+static CPUWriteMemoryFunc * const slavio_aux1_mem_write[3] = {
+ slavio_aux1_mem_writeb,
+ NULL,
+ NULL,
+};
+
+static void slavio_aux2_mem_writeb(void *opaque, target_phys_addr_t addr,
+ uint32_t val)
+{
+ MiscState *s = opaque;
+
+ val &= AUX2_PWRINTCLR | AUX2_PWROFF;
+ trace_slavio_aux2_mem_writeb(val & 0xff);
+ val |= s->aux2 & AUX2_PWRFAIL;
+ if (val & AUX2_PWRINTCLR) // Clear Power Fail int
+ val &= AUX2_PWROFF;
+ s->aux2 = val;
+ if (val & AUX2_PWROFF)
+ qemu_system_shutdown_request();
+ slavio_misc_update_irq(s);
+}
+
+static uint32_t slavio_aux2_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ MiscState *s = opaque;
+ uint32_t ret = 0;
+
+ ret = s->aux2;
+ trace_slavio_aux2_mem_readb(ret);
+ return ret;
+}
+
+static CPUReadMemoryFunc * const slavio_aux2_mem_read[3] = {
+ slavio_aux2_mem_readb,
+ NULL,
+ NULL,
+};
+
+static CPUWriteMemoryFunc * const slavio_aux2_mem_write[3] = {
+ slavio_aux2_mem_writeb,
+ NULL,
+ NULL,
+};
+
+static void apc_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
+{
+ APCState *s = opaque;
+
+ trace_apc_mem_writeb(val & 0xff);
+ qemu_irq_raise(s->cpu_halt);
+}
+
+static uint32_t apc_mem_readb(void *opaque, target_phys_addr_t addr)
+{
+ uint32_t ret = 0;
+
+ trace_apc_mem_readb(ret);
+ return ret;
+}
+
+static CPUReadMemoryFunc * const apc_mem_read[3] = {
+ apc_mem_readb,
+ NULL,
+ NULL,
+};
+
+static CPUWriteMemoryFunc * const apc_mem_write[3] = {
+ apc_mem_writeb,
+ NULL,
+ NULL,
};
static uint32_t slavio_sysctrl_mem_readl(void *opaque, target_phys_addr_t addr)
{
MiscState *s = opaque;
- uint32_t ret = 0, saddr;
+ uint32_t ret = 0;
- saddr = addr & SYSCTRL_MAXADDR;
- switch (saddr) {
+ switch (addr) {
case 0:
ret = s->sysctrl;
break;
default:
break;
}
- MISC_DPRINTF("Read system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
- ret);
+ trace_slavio_sysctrl_mem_readl(ret);
return ret;
}
uint32_t val)
{
MiscState *s = opaque;
- uint32_t saddr;
- saddr = addr & SYSCTRL_MAXADDR;
- MISC_DPRINTF("Write system control reg 0x" TARGET_FMT_plx " = %x\n", addr,
- val);
- switch (saddr) {
+ trace_slavio_sysctrl_mem_writel(val);
+ switch (addr) {
case 0:
- if (val & 1) {
- s->sysctrl = 0x2;
+ if (val & SYS_RESET) {
+ s->sysctrl = SYS_RESETSTAT;
qemu_system_reset_request();
}
break;
}
}
-static CPUReadMemoryFunc *slavio_sysctrl_mem_read[3] = {
- slavio_sysctrl_mem_readl,
- slavio_sysctrl_mem_readl,
+static CPUReadMemoryFunc * const slavio_sysctrl_mem_read[3] = {
+ NULL,
+ NULL,
slavio_sysctrl_mem_readl,
};
-static CPUWriteMemoryFunc *slavio_sysctrl_mem_write[3] = {
- slavio_sysctrl_mem_writel,
- slavio_sysctrl_mem_writel,
+static CPUWriteMemoryFunc * const slavio_sysctrl_mem_write[3] = {
+ NULL,
+ NULL,
slavio_sysctrl_mem_writel,
};
-static uint32_t slavio_led_mem_reads(void *opaque, target_phys_addr_t addr)
+static uint32_t slavio_led_mem_readw(void *opaque, target_phys_addr_t addr)
{
MiscState *s = opaque;
- uint32_t ret = 0, saddr;
+ uint32_t ret = 0;
- saddr = addr & LED_MAXADDR;
- switch (saddr) {
+ switch (addr) {
case 0:
ret = s->leds;
break;
default:
break;
}
- MISC_DPRINTF("Read diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
- ret);
+ trace_slavio_led_mem_readw(ret);
return ret;
}
-static void slavio_led_mem_writes(void *opaque, target_phys_addr_t addr,
+static void slavio_led_mem_writew(void *opaque, target_phys_addr_t addr,
uint32_t val)
{
MiscState *s = opaque;
- uint32_t saddr;
- saddr = addr & LED_MAXADDR;
- MISC_DPRINTF("Write diagnostic LED reg 0x" TARGET_FMT_plx " = %x\n", addr,
- val);
- switch (saddr) {
+ trace_slavio_led_mem_readw(val & 0xffff);
+ switch (addr) {
case 0:
- s->sysctrl = val;
+ s->leds = val;
break;
default:
break;
}
}
-static CPUReadMemoryFunc *slavio_led_mem_read[3] = {
- slavio_led_mem_reads,
- slavio_led_mem_reads,
- slavio_led_mem_reads,
+static CPUReadMemoryFunc * const slavio_led_mem_read[3] = {
+ NULL,
+ slavio_led_mem_readw,
+ NULL,
};
-static CPUWriteMemoryFunc *slavio_led_mem_write[3] = {
- slavio_led_mem_writes,
- slavio_led_mem_writes,
- slavio_led_mem_writes,
+static CPUWriteMemoryFunc * const slavio_led_mem_write[3] = {
+ NULL,
+ slavio_led_mem_writew,
+ NULL,
};
-static void slavio_misc_save(QEMUFile *f, void *opaque)
-{
- MiscState *s = opaque;
- int tmp;
- uint8_t tmp8;
-
- tmp = 0;
- qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
- qemu_put_8s(f, &s->config);
- qemu_put_8s(f, &s->aux1);
- qemu_put_8s(f, &s->aux2);
- qemu_put_8s(f, &s->diag);
- qemu_put_8s(f, &s->mctrl);
- tmp8 = s->sysctrl & 0xff;
- qemu_put_8s(f, &tmp8);
-}
+static const VMStateDescription vmstate_misc = {
+ .name ="slavio_misc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(dummy, MiscState),
+ VMSTATE_UINT8(config, MiscState),
+ VMSTATE_UINT8(aux1, MiscState),
+ VMSTATE_UINT8(aux2, MiscState),
+ VMSTATE_UINT8(diag, MiscState),
+ VMSTATE_UINT8(mctrl, MiscState),
+ VMSTATE_UINT8(sysctrl, MiscState),
+ VMSTATE_END_OF_LIST()
+ }
+};
-static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
+static int apc_init1(SysBusDevice *dev)
{
- MiscState *s = opaque;
- int tmp;
- uint8_t tmp8;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_be32s(f, &tmp);
- qemu_get_8s(f, &s->config);
- qemu_get_8s(f, &s->aux1);
- qemu_get_8s(f, &s->aux2);
- qemu_get_8s(f, &s->diag);
- qemu_get_8s(f, &s->mctrl);
- qemu_get_8s(f, &tmp8);
- s->sysctrl = (uint32_t)tmp8;
+ APCState *s = FROM_SYSBUS(APCState, dev);
+ int io;
+
+ sysbus_init_irq(dev, &s->cpu_halt);
+
+ /* Power management (APC) XXX: not a Slavio device */
+ io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
return 0;
}
-void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
- qemu_irq irq)
+static int slavio_misc_init1(SysBusDevice *dev)
{
- int slavio_misc_io_memory;
- MiscState *s;
+ MiscState *s = FROM_SYSBUS(MiscState, dev);
+ int io;
- s = qemu_mallocz(sizeof(MiscState));
- if (!s)
- return NULL;
+ sysbus_init_irq(dev, &s->irq);
+ sysbus_init_irq(dev, &s->fdc_tc);
/* 8 bit registers */
- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_misc_mem_read,
- slavio_misc_mem_write, s);
- // Slavio control
- cpu_register_physical_memory(base + 0x1800000, MISC_SIZE,
- slavio_misc_io_memory);
- // AUX 1
- cpu_register_physical_memory(base + 0x1900000, MISC_SIZE,
- slavio_misc_io_memory);
- // AUX 2
- cpu_register_physical_memory(base + 0x1910000, MISC_SIZE,
- slavio_misc_io_memory);
- // Diagnostics
- cpu_register_physical_memory(base + 0x1a00000, MISC_SIZE,
- slavio_misc_io_memory);
- // Modem control
- cpu_register_physical_memory(base + 0x1b00000, MISC_SIZE,
- slavio_misc_io_memory);
- // Power management
- cpu_register_physical_memory(power_base, MISC_SIZE, slavio_misc_io_memory);
+ /* Slavio control */
+ io = cpu_register_io_memory(slavio_cfg_mem_read,
+ slavio_cfg_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
+
+ /* Diagnostics */
+ io = cpu_register_io_memory(slavio_diag_mem_read,
+ slavio_diag_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
+
+ /* Modem control */
+ io = cpu_register_io_memory(slavio_mdm_mem_read,
+ slavio_mdm_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
/* 16 bit registers */
- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_led_mem_read,
- slavio_led_mem_write, s);
/* ss600mp diag LEDs */
- cpu_register_physical_memory(base + 0x1600000, MISC_SIZE,
- slavio_misc_io_memory);
+ io = cpu_register_io_memory(slavio_led_mem_read,
+ slavio_led_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
/* 32 bit registers */
- slavio_misc_io_memory = cpu_register_io_memory(0, slavio_sysctrl_mem_read,
- slavio_sysctrl_mem_write,
- s);
- // System control
- cpu_register_physical_memory(base + 0x1f00000, SYSCTRL_SIZE,
- slavio_misc_io_memory);
-
- s->irq = irq;
-
- register_savevm("slavio_misc", base, 1, slavio_misc_save, slavio_misc_load,
- s);
- qemu_register_reset(slavio_misc_reset, s);
- slavio_misc_reset(s);
- return s;
+ /* System control */
+ io = cpu_register_io_memory(slavio_sysctrl_mem_read,
+ slavio_sysctrl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
+
+ /* AUX 1 (Misc System Functions) */
+ io = cpu_register_io_memory(slavio_aux1_mem_read,
+ slavio_aux1_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
+
+ /* AUX 2 (Software Powerdown Control) */
+ io = cpu_register_io_memory(slavio_aux2_mem_read,
+ slavio_aux2_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
+ sysbus_init_mmio(dev, MISC_SIZE, io);
+
+ qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
+
+ return 0;
}
+
+static SysBusDeviceInfo slavio_misc_info = {
+ .init = slavio_misc_init1,
+ .qdev.name = "slavio_misc",
+ .qdev.size = sizeof(MiscState),
+ .qdev.vmsd = &vmstate_misc,
+ .qdev.reset = slavio_misc_reset,
+};
+
+static SysBusDeviceInfo apc_info = {
+ .init = apc_init1,
+ .qdev.name = "apc",
+ .qdev.size = sizeof(MiscState),
+};
+
+static void slavio_misc_register_devices(void)
+{
+ sysbus_register_withprop(&slavio_misc_info);
+ sysbus_register_withprop(&apc_info);
+}
+
+device_init(slavio_misc_register_devices)
projects / qemu.git / blobdiff