* THE SOFTWARE.
*/
-#include "sun4m.h"
#include "sysemu.h"
#include "sysbus.h"
-
-/* debug misc */
-//#define DEBUG_MISC
+#include "trace.h"
/*
* This is the auxio port, chip control and system control part of
* This also includes the PMC CPU idle controller.
*/
-#ifdef DEBUG_MISC
-#define MISC_DPRINTF(fmt, ...) \
- do { printf("MISC: " fmt , ## __VA_ARGS__); } while (0)
-#else
-#define MISC_DPRINTF(fmt, ...)
-#endif
-
typedef struct MiscState {
SysBusDevice busdev;
qemu_irq irq;
+ uint32_t dummy;
uint8_t config;
uint8_t aux1, aux2;
uint8_t diag, mctrl;
- uint32_t sysctrl;
+ uint8_t sysctrl;
uint16_t leds;
qemu_irq fdc_tc;
} MiscState;
MiscState *s = opaque;
if ((s->aux2 & AUX2_PWRFAIL) && (s->config & CFG_PWRINTEN)) {
- MISC_DPRINTF("Raise IRQ\n");
+ trace_slavio_misc_update_irq_raise();
qemu_irq_raise(s->irq);
} else {
- MISC_DPRINTF("Lower IRQ\n");
+ trace_slavio_misc_update_irq_lower();
qemu_irq_lower(s->irq);
}
}
-static void slavio_misc_reset(void *opaque)
+static void slavio_misc_reset(DeviceState *d)
{
- MiscState *s = opaque;
+ MiscState *s = container_of(d, MiscState, busdev.qdev);
// Diagnostic and system control registers not cleared in reset
s->config = s->aux1 = s->aux2 = s->mctrl = 0;
{
MiscState *s = opaque;
- MISC_DPRINTF("Power fail: %d, config: %d\n", power_failing, s->config);
+ trace_slavio_set_power_fail(power_failing, s->config);
if (power_failing && (s->config & CFG_PWRINTEN)) {
s->aux2 |= AUX2_PWRFAIL;
} else {
{
MiscState *s = opaque;
- MISC_DPRINTF("Write config %2.2x\n", val & 0xff);
+ trace_slavio_cfg_mem_writeb(val & 0xff);
s->config = val & 0xff;
slavio_misc_update_irq(s);
}
uint32_t ret = 0;
ret = s->config;
- MISC_DPRINTF("Read config %2.2x\n", ret);
+ trace_slavio_cfg_mem_readb(ret);
return ret;
}
{
MiscState *s = opaque;
- MISC_DPRINTF("Write diag %2.2x\n", val & 0xff);
+ trace_slavio_diag_mem_writeb(val & 0xff);
s->diag = val & 0xff;
}
uint32_t ret = 0;
ret = s->diag;
- MISC_DPRINTF("Read diag %2.2x\n", ret);
+ trace_slavio_diag_mem_readb(ret);
return ret;
}
{
MiscState *s = opaque;
- MISC_DPRINTF("Write modem control %2.2x\n", val & 0xff);
+ trace_slavio_mdm_mem_writeb(val & 0xff);
s->mctrl = val & 0xff;
}
uint32_t ret = 0;
ret = s->mctrl;
- MISC_DPRINTF("Read modem control %2.2x\n", ret);
+ trace_slavio_mdm_mem_readb(ret);
return ret;
}
{
MiscState *s = opaque;
- MISC_DPRINTF("Write aux1 %2.2x\n", val & 0xff);
+ trace_slavio_aux1_mem_writeb(val & 0xff);
if (val & AUX1_TC) {
// Send a pulse to floppy terminal count line
if (s->fdc_tc) {
uint32_t ret = 0;
ret = s->aux1;
- MISC_DPRINTF("Read aux1 %2.2x\n", ret);
-
+ trace_slavio_aux1_mem_readb(ret);
return ret;
}
MiscState *s = opaque;
val &= AUX2_PWRINTCLR | AUX2_PWROFF;
- MISC_DPRINTF("Write aux2 %2.2x\n", val);
+ trace_slavio_aux2_mem_writeb(val & 0xff);
val |= s->aux2 & AUX2_PWRFAIL;
if (val & AUX2_PWRINTCLR) // Clear Power Fail int
val &= AUX2_PWROFF;
uint32_t ret = 0;
ret = s->aux2;
- MISC_DPRINTF("Read aux2 %2.2x\n", ret);
-
+ trace_slavio_aux2_mem_readb(ret);
return ret;
}
{
APCState *s = opaque;
- MISC_DPRINTF("Write power management %2.2x\n", val & 0xff);
+ trace_apc_mem_writeb(val & 0xff);
qemu_irq_raise(s->cpu_halt);
}
{
uint32_t ret = 0;
- MISC_DPRINTF("Read power management %2.2x\n", ret);
+ trace_apc_mem_readb(ret);
return ret;
}
default:
break;
}
- MISC_DPRINTF("Read system control %08x\n", ret);
+ trace_slavio_sysctrl_mem_readl(ret);
return ret;
}
{
MiscState *s = opaque;
- MISC_DPRINTF("Write system control %08x\n", val);
+ trace_slavio_sysctrl_mem_writel(val);
switch (addr) {
case 0:
if (val & SYS_RESET) {
default:
break;
}
- MISC_DPRINTF("Read diagnostic LED %04x\n", ret);
+ trace_slavio_led_mem_readw(ret);
return ret;
}
{
MiscState *s = opaque;
- MISC_DPRINTF("Write diagnostic LED %04x\n", val & 0xffff);
+ trace_slavio_led_mem_readw(val & 0xffff);
switch (addr) {
case 0:
s->leds = val;
NULL,
};
-static void slavio_misc_save(QEMUFile *f, void *opaque)
-{
- MiscState *s = opaque;
- uint32_t tmp = 0;
- uint8_t tmp8;
-
- qemu_put_be32s(f, &tmp); /* ignored, was IRQ. */
- qemu_put_8s(f, &s->config);
- qemu_put_8s(f, &s->aux1);
- qemu_put_8s(f, &s->aux2);
- qemu_put_8s(f, &s->diag);
- qemu_put_8s(f, &s->mctrl);
- tmp8 = s->sysctrl & 0xff;
- qemu_put_8s(f, &tmp8);
-}
-
-static int slavio_misc_load(QEMUFile *f, void *opaque, int version_id)
-{
- MiscState *s = opaque;
- uint32_t tmp;
- uint8_t tmp8;
-
- if (version_id != 1)
- return -EINVAL;
-
- qemu_get_be32s(f, &tmp);
- qemu_get_8s(f, &s->config);
- qemu_get_8s(f, &s->aux1);
- qemu_get_8s(f, &s->aux2);
- qemu_get_8s(f, &s->diag);
- qemu_get_8s(f, &s->mctrl);
- qemu_get_8s(f, &tmp8);
- s->sysctrl = (uint32_t)tmp8;
- return 0;
-}
+static const VMStateDescription vmstate_misc = {
+ .name ="slavio_misc",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField []) {
+ VMSTATE_UINT32(dummy, MiscState),
+ VMSTATE_UINT8(config, MiscState),
+ VMSTATE_UINT8(aux1, MiscState),
+ VMSTATE_UINT8(aux2, MiscState),
+ VMSTATE_UINT8(diag, MiscState),
+ VMSTATE_UINT8(mctrl, MiscState),
+ VMSTATE_UINT8(sysctrl, MiscState),
+ VMSTATE_END_OF_LIST()
+ }
+};
static int apc_init1(SysBusDevice *dev)
{
sysbus_init_irq(dev, &s->cpu_halt);
/* Power management (APC) XXX: not a Slavio device */
- io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s);
+ io = cpu_register_io_memory(apc_mem_read, apc_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
return 0;
}
/* 8 bit registers */
/* Slavio control */
io = cpu_register_io_memory(slavio_cfg_mem_read,
- slavio_cfg_mem_write, s);
+ slavio_cfg_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* Diagnostics */
io = cpu_register_io_memory(slavio_diag_mem_read,
- slavio_diag_mem_write, s);
+ slavio_diag_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* Modem control */
io = cpu_register_io_memory(slavio_mdm_mem_read,
- slavio_mdm_mem_write, s);
+ slavio_mdm_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* 16 bit registers */
/* ss600mp diag LEDs */
io = cpu_register_io_memory(slavio_led_mem_read,
- slavio_led_mem_write, s);
+ slavio_led_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* 32 bit registers */
/* System control */
io = cpu_register_io_memory(slavio_sysctrl_mem_read,
- slavio_sysctrl_mem_write, s);
+ slavio_sysctrl_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, SYSCTRL_SIZE, io);
/* AUX 1 (Misc System Functions) */
io = cpu_register_io_memory(slavio_aux1_mem_read,
- slavio_aux1_mem_write, s);
+ slavio_aux1_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
/* AUX 2 (Software Powerdown Control) */
io = cpu_register_io_memory(slavio_aux2_mem_read,
- slavio_aux2_mem_write, s);
+ slavio_aux2_mem_write, s,
+ DEVICE_NATIVE_ENDIAN);
sysbus_init_mmio(dev, MISC_SIZE, io);
qdev_init_gpio_in(&dev->qdev, slavio_set_power_fail, 1);
- register_savevm("slavio_misc", -1, 1, slavio_misc_save, slavio_misc_load,
- s);
- qemu_register_reset(slavio_misc_reset, s);
- slavio_misc_reset(s);
return 0;
}
.init = slavio_misc_init1,
.qdev.name = "slavio_misc",
.qdev.size = sizeof(MiscState),
+ .qdev.vmsd = &vmstate_misc,
+ .qdev.reset = slavio_misc_reset,
};
static SysBusDeviceInfo apc_info = {
projects / qemu.git / blobdiff