target_ulong entry_point;
int next_irq;
int rtc_offset;
+ char *cpu_model;
} sPAPREnvironment;
#define H_SUCCESS 0
#define H_DABRX_KERNEL (1ULL<<(63-62))
#define H_DABRX_USER (1ULL<<(63-63))
-/* Each control block has to be on a 4K bondary */
+/* Each control block has to be on a 4K boundary */
#define H_CB_ALIGNMENT 4096
/* pSeries hypervisor opcodes */