typedef struct Sun4c_INTCTLState {
SysBusDevice busdev;
+ MemoryRegion iomem;
#ifdef DEBUG_IRQ_COUNT
uint64_t irq_count;
#endif
static void sun4c_check_interrupts(void *opaque);
-static uint32_t sun4c_intctl_mem_readb(void *opaque, target_phys_addr_t addr)
+static uint64_t sun4c_intctl_mem_read(void *opaque, hwaddr addr,
+ unsigned size)
{
Sun4c_INTCTLState *s = opaque;
uint32_t ret;
return ret;
}
-static void sun4c_intctl_mem_writeb(void *opaque, target_phys_addr_t addr,
- uint32_t val)
+static void sun4c_intctl_mem_write(void *opaque, hwaddr addr,
+ uint64_t val, unsigned size)
{
Sun4c_INTCTLState *s = opaque;
- DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, val);
+ DPRINTF("write reg 0x" TARGET_FMT_plx " = %x\n", addr, (unsigned)val);
val &= 0xbf;
s->reg = val;
sun4c_check_interrupts(s);
}
-static CPUReadMemoryFunc * const sun4c_intctl_mem_read[3] = {
- sun4c_intctl_mem_readb,
- NULL,
- NULL,
-};
-
-static CPUWriteMemoryFunc * const sun4c_intctl_mem_write[3] = {
- sun4c_intctl_mem_writeb,
- NULL,
- NULL,
+static const MemoryRegionOps sun4c_intctl_mem_ops = {
+ .read = sun4c_intctl_mem_read,
+ .write = sun4c_intctl_mem_write,
+ .endianness = DEVICE_NATIVE_ENDIAN,
+ .valid = {
+ .min_access_size = 1,
+ .max_access_size = 1,
+ },
};
void sun4c_pic_info(Monitor *mon, void *opaque)
}
};
-static void sun4c_intctl_reset(void *opaque)
+static void sun4c_intctl_reset(DeviceState *d)
{
- Sun4c_INTCTLState *s = opaque;
+ Sun4c_INTCTLState *s = container_of(d, Sun4c_INTCTLState, busdev.qdev);
s->reg = 1;
s->pending = 0;
static int sun4c_intctl_init1(SysBusDevice *dev)
{
Sun4c_INTCTLState *s = FROM_SYSBUS(Sun4c_INTCTLState, dev);
- int io_memory;
unsigned int i;
- io_memory = cpu_register_io_memory(sun4c_intctl_mem_read,
- sun4c_intctl_mem_write, s);
- sysbus_init_mmio(dev, INTCTL_SIZE, io_memory);
+ memory_region_init_io(&s->iomem, &sun4c_intctl_mem_ops, s,
+ "intctl", INTCTL_SIZE);
+ sysbus_init_mmio(dev, &s->iomem);
qdev_init_gpio_in(&dev->qdev, sun4c_set_irq, 8);
for (i = 0; i < MAX_PILS; i++) {
sysbus_init_irq(dev, &s->cpu_irqs[i]);
}
- vmstate_register(-1, &vmstate_sun4c_intctl, s);
- qemu_register_reset(sun4c_intctl_reset, s);
- sun4c_intctl_reset(s);
+
return 0;
}
-static SysBusDeviceInfo sun4c_intctl_info = {
- .init = sun4c_intctl_init1,
- .qdev.name = "sun4c_intctl",
- .qdev.size = sizeof(Sun4c_INTCTLState),
+static void sun4c_intctl_class_init(ObjectClass *klass, void *data)
+{
+ DeviceClass *dc = DEVICE_CLASS(klass);
+ SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
+
+ k->init = sun4c_intctl_init1;
+ dc->reset = sun4c_intctl_reset;
+ dc->vmsd = &vmstate_sun4c_intctl;
+}
+
+static TypeInfo sun4c_intctl_info = {
+ .name = "sun4c_intctl",
+ .parent = TYPE_SYS_BUS_DEVICE,
+ .instance_size = sizeof(Sun4c_INTCTLState),
+ .class_init = sun4c_intctl_class_init,
};
-static void sun4c_intctl_register_devices(void)
+static void sun4c_intctl_register_types(void)
{
- sysbus_register_withprop(&sun4c_intctl_info);
+ type_register_static(&sun4c_intctl_info);
}
-device_init(sun4c_intctl_register_devices)
+type_init(sun4c_intctl_register_types)