s->config[0x09] = 0x00; // programming i/f
pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
s->config[0x0D] = 0x0a; // latency_timer
- s->config[0x0E] = 0x00; // header_type
+ s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
pci_register_io_region(s, 0, 0x1000000, PCI_ADDRESS_SPACE_MEM,
ebus_mmio_mapfunc);
m48t59_t *nvram;
int ret, linux_boot;
unsigned int i;
- ram_addr_t ram_offset, prom_offset, vga_ram_offset;
+ ram_addr_t ram_offset, prom_offset;
long initrd_size, kernel_size;
PCIBus *pci_bus, *pci_bus2, *pci_bus3;
QEMUBH *bh;
pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL, &pci_bus2,
&pci_bus3);
isa_mem_base = VGA_BASE;
- vga_ram_offset = qemu_ram_alloc(vga_ram_size);
- pci_vga_init(pci_bus, phys_ram_base + vga_ram_offset,
- vga_ram_offset, vga_ram_size,
- 0, 0);
+ pci_vga_init(pci_bus, vga_ram_size, 0, 0);
// XXX Should be pci_bus3
pci_ebus_init(pci_bus, -1);
.name = "sun4u",
.desc = "Sun4u platform",
.init = sun4u_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
.max_cpus = 1, // XXX for now
};
.name = "sun4v",
.desc = "Sun4v platform",
.init = sun4v_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
.max_cpus = 1, // XXX for now
};
.name = "Niagara",
.desc = "Sun4v platform, Niagara",
.init = niagara_init,
- .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
.max_cpus = 1, // XXX for now
};