* This code is licensed under the GNU GPL v2.
*/
#include "hw.h"
-#include "pxa.h"
#include "devices.h"
#include "flash.h"
#include "console.h"
#define NAND_MODE_ECC_READ 0x40
#define NAND_MODE_ECC_RST 0x60
-struct tc6393xb_s {
- target_phys_addr_t target_base;
+struct TC6393xbState {
qemu_irq irq;
qemu_irq *sub_irqs;
struct {
} nand;
int nand_enable;
uint32_t nand_phys;
- struct nand_flash_s *flash;
- struct ecc_state_s ecc;
+ NANDFlashState *flash;
+ ECCState ecc;
DisplayState *ds;
- QEMUConsole *console;
ram_addr_t vram_addr;
+ uint16_t *vram_ptr;
uint32_t scr_width, scr_height; /* in pixels */
qemu_irq l3v;
unsigned blank : 1,
blanked : 1;
};
-qemu_irq *tc6393xb_gpio_in_get(struct tc6393xb_s *s)
+qemu_irq *tc6393xb_gpio_in_get(TC6393xbState *s)
{
return s->gpio_in;
}
static void tc6393xb_gpio_set(void *opaque, int line, int level)
{
-// struct tc6393xb_s *s = opaque;
+// TC6393xbState *s = opaque;
if (line > TC6393XB_GPIOS) {
printf("%s: No GPIO pin %i\n", __FUNCTION__, line);
// FIXME: how does the chip reflect the GPIO input level change?
}
-void tc6393xb_gpio_out_set(struct tc6393xb_s *s, int line,
+void tc6393xb_gpio_out_set(TC6393xbState *s, int line,
qemu_irq handler)
{
if (line >= TC6393XB_GPIOS) {
s->handler[line] = handler;
}
-static void tc6393xb_gpio_handler_update(struct tc6393xb_s *s)
+static void tc6393xb_gpio_handler_update(TC6393xbState *s)
{
uint32_t level, diff;
int bit;
s->prev_level = level;
}
-qemu_irq tc6393xb_l3v_get(struct tc6393xb_s *s)
+qemu_irq tc6393xb_l3v_get(TC6393xbState *s)
{
return s->l3v;
}
static void tc6393xb_l3v(void *opaque, int line, int level)
{
- struct tc6393xb_s *s = opaque;
+ TC6393xbState *s = opaque;
s->blank = !level;
fprintf(stderr, "L3V: %d\n", level);
}
static void tc6393xb_sub_irq(void *opaque, int line, int level) {
- struct tc6393xb_s *s = opaque;
+ TC6393xbState *s = opaque;
uint8_t isr = s->scr.ISR;
if (level)
isr |= 1 << line;
case SCR_ ##N(1): return s->scr.N[1]; \
case SCR_ ##N(2): return s->scr.N[2]
-static uint32_t tc6393xb_scr_readb(struct tc6393xb_s *s, target_phys_addr_t addr)
+static uint32_t tc6393xb_scr_readb(TC6393xbState *s, target_phys_addr_t addr)
{
switch (addr) {
case SCR_REVID:
case SCR_ ##N(1): s->scr.N[1] = value; return; \
case SCR_ ##N(2): s->scr.N[2] = value; return
-static void tc6393xb_scr_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value)
+static void tc6393xb_scr_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value)
{
switch (addr) {
SCR_REG_B(ISR);
#undef SCR_REG_L
#undef SCR_REG_A
-static void tc6393xb_nand_irq(struct tc6393xb_s *s) {
+static void tc6393xb_nand_irq(TC6393xbState *s) {
qemu_set_irq(s->sub_irqs[IRQ_TC6393_NAND],
(s->nand.imr & 0x80) && (s->nand.imr & s->nand.isr));
}
-static uint32_t tc6393xb_nand_cfg_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_cfg_readb(TC6393xbState *s, target_phys_addr_t addr) {
switch (addr) {
case NAND_CFG_COMMAND:
return s->nand_enable ? 2 : 0;
fprintf(stderr, "tc6393xb_nand_cfg: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_cfg_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_cfg_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
switch (addr) {
case NAND_CFG_COMMAND:
s->nand_enable = (value & 0x2);
(uint32_t) addr, value & 0xff);
}
-static uint32_t tc6393xb_nand_readb(struct tc6393xb_s *s, target_phys_addr_t addr) {
+static uint32_t tc6393xb_nand_readb(TC6393xbState *s, target_phys_addr_t addr) {
switch (addr) {
case NAND_DATA + 0:
case NAND_DATA + 1:
fprintf(stderr, "tc6393xb_nand: unhandled read at %08x\n", (uint32_t) addr);
return 0;
}
-static void tc6393xb_nand_writeb(struct tc6393xb_s *s, target_phys_addr_t addr, uint32_t value) {
+static void tc6393xb_nand_writeb(TC6393xbState *s, target_phys_addr_t addr, uint32_t value) {
// fprintf(stderr, "tc6393xb_nand: write at %08x: %02x\n",
// (uint32_t) addr, value & 0xff);
switch (addr) {
case NAND_DATA + 2:
case NAND_DATA + 3:
nand_setio(s->flash, value);
- s->nand.isr &= 1;
+ s->nand.isr |= 1;
tc6393xb_nand_irq(s);
return;
case NAND_MODE:
#define BITS 32
#include "tc6393xb_template.h"
-static void tc6393xb_draw_graphic(struct tc6393xb_s *s, int full_update)
+static void tc6393xb_draw_graphic(TC6393xbState *s, int full_update)
{
- switch (s->ds->depth) {
+ switch (ds_get_bits_per_pixel(s->ds)) {
case 8:
tc6393xb_draw_graphic8(s);
break;
tc6393xb_draw_graphic32(s);
break;
default:
- printf("tc6393xb: unknown depth %d\n", s->ds->depth);
+ printf("tc6393xb: unknown depth %d\n", ds_get_bits_per_pixel(s->ds));
return;
}
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
}
-static void tc6393xb_draw_blank(struct tc6393xb_s *s, int full_update)
+static void tc6393xb_draw_blank(TC6393xbState *s, int full_update)
{
int i, w;
uint8_t *d;
if (!full_update)
return;
- w = s->scr_width * ((s->ds->depth + 7) >> 3);
- d = s->ds->data;
+ w = s->scr_width * ((ds_get_bits_per_pixel(s->ds) + 7) >> 3);
+ d = ds_get_data(s->ds);
for(i = 0; i < s->scr_height; i++) {
memset(d, 0, w);
- d += s->ds->linesize;
+ d += ds_get_linesize(s->ds);
}
dpy_update(s->ds, 0, 0, s->scr_width, s->scr_height);
static void tc6393xb_update_display(void *opaque)
{
- struct tc6393xb_s *s = opaque;
+ TC6393xbState *s = opaque;
int full_update;
if (s->scr_width == 0 || s->scr_height == 0)
s->blanked = s->blank;
full_update = 1;
}
- if (s->scr_width != s->ds->width || s->scr_height != s->ds->height) {
- qemu_console_resize(s->console, s->scr_width, s->scr_height);
+ if (s->scr_width != ds_get_width(s->ds) || s->scr_height != ds_get_height(s->ds)) {
+ qemu_console_resize(s->ds, s->scr_width, s->scr_height);
full_update = 1;
}
if (s->blanked)
static uint32_t tc6393xb_readb(void *opaque, target_phys_addr_t addr) {
- struct tc6393xb_s *s = opaque;
- addr -= s->target_base;
+ TC6393xbState *s = opaque;
switch (addr >> 8) {
case 0:
}
static void tc6393xb_writeb(void *opaque, target_phys_addr_t addr, uint32_t value) {
- struct tc6393xb_s *s = opaque;
- addr -= s->target_base;
+ TC6393xbState *s = opaque;
switch (addr >> 8) {
case 0:
tc6393xb_writeb(opaque, addr + 3, value >> 24);
}
-struct tc6393xb_s *tc6393xb_init(uint32_t base, qemu_irq irq, DisplayState *ds)
+TC6393xbState *tc6393xb_init(uint32_t base, qemu_irq irq)
{
int iomemtype;
- struct tc6393xb_s *s;
- CPUReadMemoryFunc *tc6393xb_readfn[] = {
+ TC6393xbState *s;
+ CPUReadMemoryFunc * const tc6393xb_readfn[] = {
tc6393xb_readb,
tc6393xb_readw,
tc6393xb_readl,
};
- CPUWriteMemoryFunc *tc6393xb_writefn[] = {
+ CPUWriteMemoryFunc * const tc6393xb_writefn[] = {
tc6393xb_writeb,
tc6393xb_writew,
tc6393xb_writel,
};
- s = (struct tc6393xb_s *) qemu_mallocz(sizeof(struct tc6393xb_s));
- s->target_base = base;
+ s = (TC6393xbState *) qemu_mallocz(sizeof(TC6393xbState));
s->irq = irq;
s->gpio_in = qemu_allocate_irqs(tc6393xb_gpio_set, s, TC6393XB_GPIOS);
s->flash = nand_init(NAND_MFR_TOSHIBA, 0x76);
- iomemtype = cpu_register_io_memory(0, tc6393xb_readfn,
- tc6393xb_writefn, s);
- cpu_register_physical_memory(s->target_base, 0x10000, iomemtype);
-
- if (ds) {
- s->ds = ds;
- s->vram_addr = qemu_ram_alloc(0x100000);
- cpu_register_physical_memory(s->target_base + 0x100000, 0x100000, s->vram_addr);
- s->scr_width = 480;
- s->scr_height = 640;
- s->console = graphic_console_init(ds,
- tc6393xb_update_display,
- NULL, /* invalidate */
- NULL, /* screen_dump */
- NULL, /* text_update */
- s);
- }
+ iomemtype = cpu_register_io_memory(tc6393xb_readfn,
+ tc6393xb_writefn, s, DEVICE_NATIVE_ENDIAN);
+ cpu_register_physical_memory(base, 0x10000, iomemtype);
+
+ s->vram_addr = qemu_ram_alloc(NULL, "tc6393xb.vram", 0x100000);
+ s->vram_ptr = qemu_get_ram_ptr(s->vram_addr);
+ cpu_register_physical_memory(base + 0x100000, 0x100000, s->vram_addr);
+ s->scr_width = 480;
+ s->scr_height = 640;
+ s->ds = graphic_console_init(tc6393xb_update_display,
+ NULL, /* invalidate */
+ NULL, /* screen_dump */
+ NULL, /* text_update */
+ s);
return s;
}
projects / qemu.git / blobdiff