aio / timers: Convert rtc_clock to be a QEMUClockType

[qemu.git] / hw / timer / pl031.c

diff --git a/hw/timer/pl031.c b/hw/timer/pl031.c
index 764940be7eb4fcb63d8aac1202189adf966ca664..e398a6768a853528852c96626ef7306e7781d18f 100644 (file)
--- a/hw/timer/pl031.c
+++ b/hw/timer/pl031.c
@@ -33,8 +33,12 @@ do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
 #define RTC_MIS     0x18    /* Masked interrupt status register */
 #define RTC_ICR     0x1c    /* Interrupt clear register */
 
-typedef struct {
-    SysBusDevice busdev;
+#define TYPE_PL031 "pl031"
+#define PL031(obj) OBJECT_CHECK(PL031State, (obj), TYPE_PL031)
+
+typedef struct PL031State {
+    SysBusDevice parent_obj;
+
     MemoryRegion iomem;
     QEMUTimer *timer;
     qemu_irq irq;
@@ -51,34 +55,34 @@ typedef struct {
     uint32_t cr;
     uint32_t im;
     uint32_t is;
-} pl031_state;
+} PL031State;
 
 static const unsigned char pl031_id[] = {
     0x31, 0x10, 0x14, 0x00,         /* Device ID        */
     0x0d, 0xf0, 0x05, 0xb1          /* Cell ID      */
 };
 
-static void pl031_update(pl031_state *s)
+static void pl031_update(PL031State *s)
 {
     qemu_set_irq(s->irq, s->is & s->im);
 }
 
 static void pl031_interrupt(void * opaque)
 {
-    pl031_state *s = (pl031_state *)opaque;
+    PL031State *s = (PL031State *)opaque;
 
     s->is = 1;
     DPRINTF("Alarm raised\n");
     pl031_update(s);
 }
 
-static uint32_t pl031_get_count(pl031_state *s)
+static uint32_t pl031_get_count(PL031State *s)
 {
-    int64_t now = qemu_get_clock_ns(rtc_clock);
+    int64_t now = qemu_clock_get_ns(rtc_clock);
     return s->tick_offset + now / get_ticks_per_sec();
 }
 
-static void pl031_set_alarm(pl031_state *s)
+static void pl031_set_alarm(PL031State *s)
 {
     uint32_t ticks;
 
@@ -90,7 +94,7 @@ static void pl031_set_alarm(pl031_state *s)
         qemu_del_timer(s->timer);
         pl031_interrupt(s);
     } else {
-        int64_t now = qemu_get_clock_ns(rtc_clock);
+        int64_t now = qemu_clock_get_ns(rtc_clock);
         qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
     }
 }
@@ -98,7 +102,7 @@ static void pl031_set_alarm(pl031_state *s)
 static uint64_t pl031_read(void *opaque, hwaddr offset,
                            unsigned size)
 {
-    pl031_state *s = (pl031_state *)opaque;
+    PL031State *s = (PL031State *)opaque;
 
     if (offset >= 0xfe0  &&  offset < 0x1000)
         return pl031_id[(offset - 0xfe0) >> 2];
@@ -136,7 +140,7 @@ static uint64_t pl031_read(void *opaque, hwaddr offset,
 static void pl031_write(void * opaque, hwaddr offset,
                         uint64_t value, unsigned size)
 {
-    pl031_state *s = (pl031_state *)opaque;
+    PL031State *s = (PL031State *)opaque;
 
 
     switch (offset) {
@@ -189,35 +193,36 @@ static const MemoryRegionOps pl031_ops = {
 
 static int pl031_init(SysBusDevice *dev)
 {
-    pl031_state *s = FROM_SYSBUS(pl031_state, dev);
+    PL031State *s = PL031(dev);
     struct tm tm;
 
-    memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
+    memory_region_init_io(&s->iomem, OBJECT(s), &pl031_ops, s, "pl031", 0x1000);
     sysbus_init_mmio(dev, &s->iomem);
 
     sysbus_init_irq(dev, &s->irq);
     qemu_get_timedate(&tm, 0);
-    s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
+    s->tick_offset = mktimegm(&tm) -
+        qemu_clock_get_ns(rtc_clock) / get_ticks_per_sec();
 
-    s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
+    s->timer = timer_new_ns(rtc_clock, pl031_interrupt, s);
     return 0;
 }
 
 static void pl031_pre_save(void *opaque)
 {
-    pl031_state *s = opaque;
+    PL031State *s = opaque;
 
     /* tick_offset is base_time - rtc_clock base time.  Instead, we want to
      * store the base time relative to the vm_clock for backwards-compatibility.  */
-    int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
     s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
 }
 
 static int pl031_post_load(void *opaque, int version_id)
 {
-    pl031_state *s = opaque;
+    PL031State *s = opaque;
 
-    int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
+    int64_t delta = qemu_clock_get_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
     s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
     pl031_set_alarm(s);
     return 0;
@@ -230,12 +235,12 @@ static const VMStateDescription vmstate_pl031 = {
     .pre_save = pl031_pre_save,
     .post_load = pl031_post_load,
     .fields = (VMStateField[]) {
-        VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
-        VMSTATE_UINT32(mr, pl031_state),
-        VMSTATE_UINT32(lr, pl031_state),
-        VMSTATE_UINT32(cr, pl031_state),
-        VMSTATE_UINT32(im, pl031_state),
-        VMSTATE_UINT32(is, pl031_state),
+        VMSTATE_UINT32(tick_offset_vmstate, PL031State),
+        VMSTATE_UINT32(mr, PL031State),
+        VMSTATE_UINT32(lr, PL031State),
+        VMSTATE_UINT32(cr, PL031State),
+        VMSTATE_UINT32(im, PL031State),
+        VMSTATE_UINT32(is, PL031State),
         VMSTATE_END_OF_LIST()
     }
 };
@@ -251,9 +256,9 @@ static void pl031_class_init(ObjectClass *klass, void *data)
 }
 
 static const TypeInfo pl031_info = {
-    .name          = "pl031",
+    .name          = TYPE_PL031,
     .parent        = TYPE_SYS_BUS_DEVICE,
-    .instance_size = sizeof(pl031_state),
+    .instance_size = sizeof(PL031State),
     .class_init    = pl031_class_init,
 };