user: Restore debug usage message for '-d ?' in user mode emulation

[qemu.git] / hw / tusb6010.c

diff --git a/hw/tusb6010.c b/hw/tusb6010.c
index d6847d012d7f92fa6b0e1e99999a815f70d79218..ccd01ad4437b5c351504134c17dfd7430ef4de8d 100644 (file)
--- a/hw/tusb6010.c
+++ b/hw/tusb6010.c
@@ -16,8 +16,7 @@
  * GNU General Public License for more details.
  *
  * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
  */
 #include "qemu-common.h"
 #include "qemu-timer.h"
@@ -26,10 +25,10 @@
 #include "irq.h"
 #include "devices.h"
 
-struct tusb_s {
+struct TUSBState {
     int iomemtype[2];
     qemu_irq irq;
-    struct musb_s *musb;
+    MUSBState *musb;
     QEMUTimer *otg_timer;
     QEMUTimer *pwr_timer;
 
@@ -235,17 +234,17 @@ struct tusb_s {
 #define TUSB_EP_CONFIG_XFR_SIZE(v)     ((v) & 0x7fffffff)
 #define TUSB_PROD_TEST_RESET_VAL       0xa596
 
-int tusb6010_sync_io(struct tusb_s *s)
+int tusb6010_sync_io(TUSBState *s)
 {
     return s->iomemtype[0];
 }
 
-int tusb6010_async_io(struct tusb_s *s)
+int tusb6010_async_io(TUSBState *s)
 {
     return s->iomemtype[1];
 }
 
-static void tusb_intr_update(struct tusb_s *s)
+static void tusb_intr_update(TUSBState *s)
 {
     if (s->control_config & TUSB_INT_CTRL_CONF_INT_POLARITY)
         qemu_set_irq(s->irq, s->intr & ~s->mask & s->intr_ok);
@@ -253,7 +252,7 @@ static void tusb_intr_update(struct tusb_s *s)
         qemu_set_irq(s->irq, (!(s->intr & ~s->mask)) & s->intr_ok);
 }
 
-static void tusb_usbip_intr_update(struct tusb_s *s)
+static void tusb_usbip_intr_update(TUSBState *s)
 {
     /* TX interrupt in the MUSB */
     if (s->usbip_intr & 0x0000ffff & ~s->usbip_mask)
@@ -272,7 +271,7 @@ static void tusb_usbip_intr_update(struct tusb_s *s)
     tusb_intr_update(s);
 }
 
-static void tusb_dma_intr_update(struct tusb_s *s)
+static void tusb_dma_intr_update(TUSBState *s)
 {
     if (s->dma_intr & ~s->dma_mask)
         s->intr |= TUSB_INT_SRC_TXRX_DMA_DONE;
@@ -282,17 +281,17 @@ static void tusb_dma_intr_update(struct tusb_s *s)
     tusb_intr_update(s);
 }
 
-static void tusb_gpio_intr_update(struct tusb_s *s)
+static void tusb_gpio_intr_update(TUSBState *s)
 {
     /* TODO: How is this signalled?  */
 }
 
-extern CPUReadMemoryFunc *musb_read[];
-extern CPUWriteMemoryFunc *musb_write[];
+extern CPUReadMemoryFunc * const musb_read[];
+extern CPUWriteMemoryFunc * const musb_write[];
 
 static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -309,7 +308,7 @@ static uint32_t tusb_async_readb(void *opaque, target_phys_addr_t addr)
 
 static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -326,7 +325,7 @@ static uint32_t tusb_async_readh(void *opaque, target_phys_addr_t addr)
 
 static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     int offset = addr & 0xfff;
     int epnum;
     uint32_t ret;
@@ -426,7 +425,6 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
         return s->rx_config[epnum];
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
         return 0x00000000;     /* TODO */
     case TUSB_WAIT_COUNT:
         return 0x00;           /* TODO */
@@ -451,7 +449,7 @@ static uint32_t tusb_async_readw(void *opaque, target_phys_addr_t addr)
 static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -472,7 +470,7 @@ static void tusb_async_writeb(void *opaque, target_phys_addr_t addr,
 static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     switch (addr & 0xfff) {
     case TUSB_BASE_OFFSET ... (TUSB_BASE_OFFSET | 0x1ff):
@@ -493,7 +491,7 @@ static void tusb_async_writeh(void *opaque, target_phys_addr_t addr,
 static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
                 uint32_t value)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     int offset = addr & 0xfff;
     int epnum;
 
@@ -513,8 +511,7 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
         s->dev_config = value;
         s->host_mode = (value & TUSB_DEV_CONF_USB_HOST_MODE);
         if (value & TUSB_DEV_CONF_PROD_TEST_MODE)
-            cpu_abort(cpu_single_env, "%s: Product Test mode not allowed\n",
-                            __FUNCTION__);
+            hw_error("%s: Product Test mode not allowed\n", __FUNCTION__);
         break;
 
     case TUSB_PHY_OTG_CTRL_ENABLE:
@@ -523,9 +520,9 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
     case TUSB_DEV_OTG_TIMER:
         s->otg_timer_val = value;
         if (value & TUSB_DEV_OTG_TIMER_ENABLE)
-            qemu_mod_timer(s->otg_timer, qemu_get_clock(vm_clock) +
+            qemu_mod_timer(s->otg_timer, qemu_get_clock_ns(vm_clock) +
                             muldiv64(TUSB_DEV_OTG_TIMER_VAL(value),
-                                    ticks_per_sec, TUSB_DEVCLOCK));
+                                     get_ticks_per_sec(), TUSB_DEVCLOCK));
         else
             qemu_del_timer(s->otg_timer);
         break;
@@ -632,7 +629,6 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
         break;
     case TUSB_EP_MAX_PACKET_SIZE_OFFSET ...
             (TUSB_EP_MAX_PACKET_SIZE_OFFSET + 0x3b):
-        epnum = (offset - TUSB_EP_MAX_PACKET_SIZE_OFFSET) >> 2;
         return;                /* TODO */
     case TUSB_WAIT_COUNT:
         return;                /* TODO */
@@ -651,13 +647,13 @@ static void tusb_async_writew(void *opaque, target_phys_addr_t addr,
     }
 }
 
-static CPUReadMemoryFunc *tusb_async_readfn[] = {
+static CPUReadMemoryFunc * const tusb_async_readfn[] = {
     tusb_async_readb,
     tusb_async_readh,
     tusb_async_readw,
 };
 
-static CPUWriteMemoryFunc *tusb_async_writefn[] = {
+static CPUWriteMemoryFunc * const tusb_async_writefn[] = {
     tusb_async_writeb,
     tusb_async_writeh,
     tusb_async_writew,
@@ -665,7 +661,7 @@ static CPUWriteMemoryFunc *tusb_async_writefn[] = {
 
 static void tusb_otg_tick(void *opaque)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     s->otg_timer_val = 0;
     s->intr |= TUSB_INT_SRC_OTG_TIMEOUT;
@@ -674,7 +670,7 @@ static void tusb_otg_tick(void *opaque)
 
 static void tusb_power_tick(void *opaque)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
 
     if (s->power) {
         s->intr_ok = ~0;
@@ -684,7 +680,7 @@ static void tusb_power_tick(void *opaque)
 
 static void tusb_musb_core_intr(void *opaque, int source, int level)
 {
-    struct tusb_s *s = (struct tusb_s *) opaque;
+    TUSBState *s = (TUSBState *) opaque;
     uint16_t otg_status = s->otg_status;
 
     switch (source) {
@@ -731,9 +727,9 @@ static void tusb_musb_core_intr(void *opaque, int source, int level)
     }
 }
 
-struct tusb_s *tusb6010_init(qemu_irq intr)
+TUSBState *tusb6010_init(qemu_irq intr)
 {
-    struct tusb_s *s = qemu_mallocz(sizeof(*s));
+    TUSBState *s = qemu_mallocz(sizeof(*s));
 
     s->test_reset = TUSB_PROD_TEST_RESET_VAL;
     s->host_mode = 0;
@@ -743,18 +739,18 @@ struct tusb_s *tusb6010_init(qemu_irq intr)
     s->mask = 0xffffffff;
     s->intr = 0x00000000;
     s->otg_timer_val = 0;
-    s->iomemtype[1] = cpu_register_io_memory(0, tusb_async_readfn,
-                    tusb_async_writefn, s);
+    s->iomemtype[1] = cpu_register_io_memory(tusb_async_readfn,
+                    tusb_async_writefn, s, DEVICE_NATIVE_ENDIAN);
     s->irq = intr;
-    s->otg_timer = qemu_new_timer(vm_clock, tusb_otg_tick, s);
-    s->pwr_timer = qemu_new_timer(vm_clock, tusb_power_tick, s);
+    s->otg_timer = qemu_new_timer_ns(vm_clock, tusb_otg_tick, s);
+    s->pwr_timer = qemu_new_timer_ns(vm_clock, tusb_power_tick, s);
     s->musb = musb_init(qemu_allocate_irqs(tusb_musb_core_intr, s,
                             __musb_irq_max));
 
     return s;
 }
 
-void tusb6010_power(struct tusb_s *s, int on)
+void tusb6010_power(TUSBState *s, int on)
 {
     if (!on)
         s->power = 0;
@@ -765,6 +761,6 @@ void tusb6010_power(struct tusb_s *s, int on)
         s->intr_ok = 0;
         tusb_intr_update(s);
         qemu_mod_timer(s->pwr_timer,
-                        qemu_get_clock(vm_clock) + ticks_per_sec / 2);
+                       qemu_get_clock_ns(vm_clock) + get_ticks_per_sec() / 2);
     }
 }