} XHCIInterrupter;
struct XHCIState {
- PCIDevice pci_dev;
+ /*< private >*/
+ PCIDevice parent_obj;
+ /*< public >*/
+
USBBus bus;
qemu_irq irq;
MemoryRegion mem;
XHCIRing cmd_ring;
};
+#define TYPE_XHCI "nec-usb-xhci"
+
+#define XHCI(obj) \
+ OBJECT_CHECK(XHCIState, (obj), TYPE_XHCI)
+
typedef struct XHCIEvRingSeg {
uint32_t addr_low;
uint32_t addr_high;
[CC_SPLIT_TRANSACTION_ERROR] = "CC_SPLIT_TRANSACTION_ERROR",
};
+static const char *ep_state_names[] = {
+ [EP_DISABLED] = "disabled",
+ [EP_RUNNING] = "running",
+ [EP_HALTED] = "halted",
+ [EP_STOPPED] = "stopped",
+ [EP_ERROR] = "error",
+};
+
static const char *lookup_name(uint32_t index, const char **list, uint32_t llen)
{
if (index >= llen || list[index] == NULL) {
ARRAY_SIZE(TRBCCode_names));
}
+static const char *ep_state_name(uint32_t state)
+{
+ return lookup_name(state, ep_state_names,
+ ARRAY_SIZE(ep_state_names));
+}
+
static uint64_t xhci_mfindex_get(XHCIState *xhci)
{
- int64_t now = qemu_get_clock_ns(vm_clock);
+ int64_t now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
return (now - xhci->mfindex_start) / 125000;
}
int64_t now;
if ((xhci->usbcmd & bits) == bits) {
- now = qemu_get_clock_ns(vm_clock);
+ now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
mfindex = ((now - xhci->mfindex_start) / 125000) & 0x3fff;
left = 0x4000 - mfindex;
- qemu_mod_timer(xhci->mfwrap_timer, now + left * 125000);
+ timer_mod(xhci->mfwrap_timer, now + left * 125000);
} else {
- qemu_del_timer(xhci->mfwrap_timer);
+ timer_del(xhci->mfwrap_timer);
}
}
assert((len % sizeof(uint32_t)) == 0);
- pci_dma_read(&xhci->pci_dev, addr, buf, len);
+ pci_dma_read(PCI_DEVICE(xhci), addr, buf, len);
for (i = 0; i < (len / sizeof(uint32_t)); i++) {
buf[i] = le32_to_cpu(buf[i]);
for (i = 0; i < (len / sizeof(uint32_t)); i++) {
tmp[i] = cpu_to_le32(buf[i]);
}
- pci_dma_write(&xhci->pci_dev, addr, tmp, len);
+ pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len);
}
static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport)
static void xhci_intx_update(XHCIState *xhci)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
int level = 0;
- if (msix_enabled(&xhci->pci_dev) ||
- msi_enabled(&xhci->pci_dev)) {
+ if (msix_enabled(pci_dev) ||
+ msi_enabled(pci_dev)) {
return;
}
static void xhci_msix_update(XHCIState *xhci, int v)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
bool enabled;
- if (!msix_enabled(&xhci->pci_dev)) {
+ if (!msix_enabled(pci_dev)) {
return;
}
if (enabled) {
trace_usb_xhci_irq_msix_use(v);
- msix_vector_use(&xhci->pci_dev, v);
+ msix_vector_use(pci_dev, v);
xhci->intr[v].msix_used = true;
} else {
trace_usb_xhci_irq_msix_unuse(v);
- msix_vector_unuse(&xhci->pci_dev, v);
+ msix_vector_unuse(pci_dev, v);
xhci->intr[v].msix_used = false;
}
}
static void xhci_intr_raise(XHCIState *xhci, int v)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
+
xhci->intr[v].erdp_low |= ERDP_EHB;
xhci->intr[v].iman |= IMAN_IP;
xhci->usbsts |= USBSTS_EINT;
return;
}
- if (msix_enabled(&xhci->pci_dev)) {
+ if (msix_enabled(pci_dev)) {
trace_usb_xhci_irq_msix(v);
- msix_notify(&xhci->pci_dev, v);
+ msix_notify(pci_dev, v);
return;
}
- if (msi_enabled(&xhci->pci_dev)) {
+ if (msi_enabled(pci_dev)) {
trace_usb_xhci_irq_msi(v);
- msi_notify(&xhci->pci_dev, v);
+ msi_notify(pci_dev, v);
return;
}
static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCIInterrupter *intr = &xhci->intr[v];
XHCITRB ev_trb;
dma_addr_t addr;
ev_trb.status, ev_trb.control);
addr = intr->er_start + TRB_SIZE*intr->er_ep_idx;
- pci_dma_write(&xhci->pci_dev, addr, &ev_trb, TRB_SIZE);
+ pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE);
intr->er_ep_idx++;
if (intr->er_ep_idx >= intr->er_size) {
static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb,
dma_addr_t *addr)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
+
while (1) {
TRBType type;
- pci_dma_read(&xhci->pci_dev, ring->dequeue, trb, TRB_SIZE);
+ pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE);
trb->addr = ring->dequeue;
trb->ccs = ring->ccs;
le64_to_cpus(&trb->parameter);
static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCITRB trb;
int length = 0;
dma_addr_t dequeue = ring->dequeue;
while (1) {
TRBType type;
- pci_dma_read(&xhci->pci_dev, dequeue, &trb, TRB_SIZE);
+ pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE);
le64_to_cpus(&trb.parameter);
le32_to_cpus(&trb.status);
le32_to_cpus(&trb.control);
return;
}
dma_addr_t erstba = xhci_addr64(intr->erstba_low, intr->erstba_high);
- pci_dma_read(&xhci->pci_dev, erstba, &seg, sizeof(seg));
+ pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg));
le32_to_cpus(&seg.addr_low);
le32_to_cpus(&seg.addr_high);
le32_to_cpus(&seg.size);
{
trace_usb_xhci_run();
xhci->usbsts &= ~USBSTS_HCH;
- xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
+ xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
}
static void xhci_stop(XHCIState *xhci)
if (sctx->sct == -1) {
xhci_dma_read_u32s(epctx->xhci, sctx->pctx, ctx, sizeof(ctx));
- fprintf(stderr, "%s: init sctx #%d @ " DMA_ADDR_FMT ": %08x %08x\n",
- __func__, streamid, sctx->pctx, ctx[0], ctx[1]);
sct = (ctx[0] >> 1) & 0x07;
if (epctx->lsa && sct != 1) {
*cc_error = CC_INVALID_STREAM_TYPE_ERROR;
}
xhci_dma_write_u32s(xhci, epctx->pctx, ctx, sizeof(ctx));
+ if (epctx->state != state) {
+ trace_usb_xhci_ep_state(epctx->slotid, epctx->epid,
+ ep_state_name(epctx->state),
+ ep_state_name(state));
+ }
epctx->state = state;
}
for (i = 0; i < ARRAY_SIZE(epctx->transfers); i++) {
usb_packet_init(&epctx->transfers[i].packet);
}
- epctx->kick_timer = qemu_new_timer_ns(vm_clock, xhci_ep_kick_timer, epctx);
+ epctx->kick_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_ep_kick_timer, epctx);
return epctx;
}
XHCIEPContext *epctx = t->xhci->slots[t->slotid-1].eps[t->epid-1];
if (epctx) {
epctx->retry = NULL;
- qemu_del_timer(epctx->kick_timer);
+ timer_del(epctx->kick_timer);
}
t->running_retry = 0;
}
xhci_set_ep_state(xhci, epctx, NULL, EP_DISABLED);
- qemu_free_timer(epctx->kick_timer);
+ timer_free(epctx->kick_timer);
g_free(epctx);
slot->eps[epid-1] = NULL;
{
XHCISlot *slot;
XHCIEPContext *epctx;
- USBDevice *dev;
trace_usb_xhci_ep_reset(slotid, epid);
assert(slotid >= 1 && slotid <= xhci->numslots);
ep |= 0x80;
}
- dev = xhci->slots[slotid-1].uport->dev;
- if (!dev) {
+ if (!xhci->slots[slotid-1].uport ||
+ !xhci->slots[slotid-1].uport->dev) {
return CC_USB_TRANSACTION_ERROR;
}
int i;
xfer->int_req = false;
- pci_dma_sglist_init(&xfer->sgl, &xhci->pci_dev, xfer->trb_count);
+ pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count);
for (i = 0; i < xfer->trb_count; i++) {
XHCITRB *trb = &xfer->trbs[i];
dma_addr_t addr;
trace_usb_xhci_xfer_error(xfer, xfer->packet.status);
switch (xfer->packet.status) {
case USB_RET_NODEV:
+ case USB_RET_IOERROR:
xfer->status = CC_USB_TRANSACTION_ERROR;
xhci_xfer_report(xfer);
xhci_stall_ep(xfer);
XHCIEPContext *epctx, uint64_t mfindex)
{
if (xfer->mfindex_kick > mfindex) {
- qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock) +
+ timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) +
(xfer->mfindex_kick - mfindex) * 125000);
xfer->running_retry = 1;
} else {
epctx->mfindex_last = xfer->mfindex_kick;
- qemu_del_timer(epctx->kick_timer);
+ timer_del(epctx->kick_timer);
xfer->running_retry = 0;
}
}
assert(slotid >= 1 && slotid <= xhci->numslots);
dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high);
- poctx = ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid);
+ poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid);
ictx = xhci_mask64(pictx);
octx = xhci_mask64(poctx);
/* TODO: actually implement real values here */
bw_ctx[0] = 0;
memset(&bw_ctx[1], 80, xhci->numports); /* 80% */
- pci_dma_write(&xhci->pci_dev, ctx, bw_ctx, sizeof(bw_ctx));
+ pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx));
return CC_SUCCESS;
}
static void xhci_via_challenge(XHCIState *xhci, uint64_t addr)
{
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
uint32_t buf[8];
uint32_t obuf[8];
dma_addr_t paddr = xhci_mask64(addr);
- pci_dma_read(&xhci->pci_dev, paddr, &buf, 32);
+ pci_dma_read(pci_dev, paddr, &buf, 32);
memcpy(obuf, buf, sizeof(obuf));
obuf[7] = obuf[2] ^ obuf[3] ^ 0x65866593;
}
- pci_dma_write(&xhci->pci_dev, paddr, &obuf, 32);
+ pci_dma_write(pci_dev, paddr, &obuf, 32);
}
static void xhci_process_commands(XHCIState *xhci)
xhci_port_notify(port, PORTSC_CSC);
}
-static void xhci_port_reset(XHCIPort *port)
+static void xhci_port_reset(XHCIPort *port, bool warm_reset)
{
trace_usb_xhci_port_reset(port->portnr);
usb_device_reset(port->uport->dev);
switch (port->uport->dev->speed) {
+ case USB_SPEED_SUPER:
+ if (warm_reset) {
+ port->portsc |= PORTSC_WRC;
+ }
+ /* fall through */
case USB_SPEED_LOW:
case USB_SPEED_FULL:
case USB_SPEED_HIGH:
static void xhci_reset(DeviceState *dev)
{
- XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev.qdev, dev);
+ XHCIState *xhci = XHCI(dev);
int i;
trace_usb_xhci_reset();
xhci->intr[i].ev_buffer_get = 0;
}
- xhci->mfindex_start = qemu_get_clock_ns(vm_clock);
+ xhci->mfindex_start = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
xhci_mfwrap_update(xhci);
}
switch (reg) {
case 0x00: /* PORTSC */
/* write-1-to-start bits */
+ if (val & PORTSC_WPR) {
+ xhci_port_reset(port, true);
+ break;
+ }
if (val & PORTSC_PR) {
- xhci_port_reset(port);
+ xhci_port_reset(port, false);
break;
}
uint64_t val, unsigned size)
{
XHCIState *xhci = ptr;
+ DeviceState *d = DEVICE(ptr);
trace_usb_xhci_oper_write(reg, val);
xhci->usbcmd = val & 0xc0f;
xhci_mfwrap_update(xhci);
if (val & USBCMD_HCRST) {
- xhci_reset(&xhci->pci_dev.qdev);
+ xhci_reset(d);
}
xhci_intx_update(xhci);
break;
.wakeup_endpoint = xhci_wakeup_endpoint,
};
-static void usb_xhci_init(XHCIState *xhci, DeviceState *dev)
+static void usb_xhci_init(XHCIState *xhci)
{
+ DeviceState *dev = DEVICE(xhci);
XHCIPort *port;
int i, usbports, speedmask;
usbports = MAX(xhci->numports_2, xhci->numports_3);
xhci->numports = xhci->numports_2 + xhci->numports_3;
- usb_bus_new(&xhci->bus, &xhci_bus_ops, &xhci->pci_dev.qdev);
+ usb_bus_new(&xhci->bus, &xhci_bus_ops, dev);
for (i = 0; i < usbports; i++) {
speedmask = 0;
{
int i, ret;
- XHCIState *xhci = DO_UPCAST(XHCIState, pci_dev, dev);
+ XHCIState *xhci = XHCI(dev);
- xhci->pci_dev.config[PCI_CLASS_PROG] = 0x30; /* xHCI */
- xhci->pci_dev.config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
- xhci->pci_dev.config[PCI_CACHE_LINE_SIZE] = 0x10;
- xhci->pci_dev.config[0x60] = 0x30; /* release number */
+ dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */
+ dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */
+ dev->config[PCI_CACHE_LINE_SIZE] = 0x10;
+ dev->config[0x60] = 0x30; /* release number */
- usb_xhci_init(xhci, &dev->qdev);
+ usb_xhci_init(xhci);
if (xhci->numintrs > MAXINTRS) {
xhci->numintrs = MAXINTRS;
xhci->numslots = 1;
}
- xhci->mfwrap_timer = qemu_new_timer_ns(vm_clock, xhci_mfwrap_timer, xhci);
+ xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci);
- xhci->irq = xhci->pci_dev.irq[0];
+ xhci->irq = dev->irq[0];
- memory_region_init(&xhci->mem, "xhci", LEN_REGS);
- memory_region_init_io(&xhci->mem_cap, &xhci_cap_ops, xhci,
+ memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS);
+ memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci,
"capabilities", LEN_CAP);
- memory_region_init_io(&xhci->mem_oper, &xhci_oper_ops, xhci,
+ memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci,
"operational", 0x400);
- memory_region_init_io(&xhci->mem_runtime, &xhci_runtime_ops, xhci,
+ memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci,
"runtime", LEN_RUNTIME);
- memory_region_init_io(&xhci->mem_doorbell, &xhci_doorbell_ops, xhci,
+ memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci,
"doorbell", LEN_DOORBELL);
memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap);
XHCIPort *port = &xhci->ports[i];
uint32_t offset = OFF_OPER + 0x400 + 0x10 * i;
port->xhci = xhci;
- memory_region_init_io(&port->mem, &xhci_port_ops, port,
+ memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port,
port->name, 0x10);
memory_region_add_subregion(&xhci->mem, offset, &port->mem);
}
- pci_register_bar(&xhci->pci_dev, 0,
+ pci_register_bar(dev, 0,
PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64,
&xhci->mem);
- ret = pcie_endpoint_cap_init(&xhci->pci_dev, 0xa0);
+ ret = pcie_endpoint_cap_init(dev, 0xa0);
assert(ret >= 0);
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI)) {
- msi_init(&xhci->pci_dev, 0x70, xhci->numintrs, true, false);
+ msi_init(dev, 0x70, xhci->numintrs, true, false);
}
if (xhci->flags & (1 << XHCI_FLAG_USE_MSI_X)) {
- msix_init(&xhci->pci_dev, xhci->numintrs,
+ msix_init(dev, xhci->numintrs,
&xhci->mem, 0, OFF_MSIX_TABLE,
&xhci->mem, 0, OFF_MSIX_PBA,
0x90);
static int usb_xhci_post_load(void *opaque, int version_id)
{
XHCIState *xhci = opaque;
+ PCIDevice *pci_dev = PCI_DEVICE(xhci);
XHCISlot *slot;
XHCIEPContext *epctx;
dma_addr_t dcbaap, pctx;
continue;
}
slot->ctx =
- xhci_mask64(ldq_le_pci_dma(&xhci->pci_dev, dcbaap + 8*slotid));
+ xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid));
xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx));
slot->uport = xhci_lookup_uport(xhci, slot_ctx);
assert(slot->uport && slot->uport->dev);
epctx->state = state;
if (state == EP_RUNNING) {
/* kick endpoint after vmload is finished */
- qemu_mod_timer(epctx->kick_timer, qemu_get_clock_ns(vm_clock));
+ timer_mod(epctx->kick_timer, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL));
}
}
}
for (intr = 0; intr < xhci->numintrs; intr++) {
if (xhci->intr[intr].msix_used) {
- msix_vector_use(&xhci->pci_dev, intr);
+ msix_vector_use(pci_dev, intr);
} else {
- msix_vector_unuse(&xhci->pci_dev, intr);
+ msix_vector_unuse(pci_dev, intr);
}
}
.version_id = 1,
.post_load = usb_xhci_post_load,
.fields = (VMStateField[]) {
- VMSTATE_PCIE_DEVICE(pci_dev, XHCIState),
- VMSTATE_MSIX(pci_dev, XHCIState),
+ VMSTATE_PCIE_DEVICE(parent_obj, XHCIState),
+ VMSTATE_MSIX(parent_obj, XHCIState),
VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1,
vmstate_xhci_port, XHCIPort),
dc->vmsd = &vmstate_xhci;
dc->props = xhci_properties;
dc->reset = xhci_reset;
+ set_bit(DEVICE_CATEGORY_USB, dc->categories);
k->init = usb_xhci_initfn;
k->vendor_id = PCI_VENDOR_ID_NEC;
k->device_id = PCI_DEVICE_ID_NEC_UPD720200;
}
static const TypeInfo xhci_info = {
- .name = "nec-usb-xhci",
+ .name = TYPE_XHCI,
.parent = TYPE_PCI_DEVICE,
.instance_size = sizeof(XHCIState),
.class_init = xhci_class_init,
projects / qemu.git / blobdiff