EST_FETCHENTRY,
EST_FETCHQH,
EST_FETCHITD,
+ EST_FETCHSITD,
EST_ADVANCEQUEUE,
EST_FETCHQTD,
EST_EXECUTE,
get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
}
+static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
+ EHCIsitd *sitd)
+{
+ trace_usb_ehci_sitd(addr, sitd->next,
+ (bool)(sitd->results & SITD_RESULTS_ACTIVE));
+}
+
/* queue management */
static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
{
EHCIQueue *q;
- q = qemu_mallocz(sizeof(*q));
+ q = g_malloc0(sizeof(*q));
q->ehci = ehci;
q->async_schedule = async;
QTAILQ_INSERT_HEAD(&ehci->queues, q, next);
usb_cancel_packet(&q->packet);
}
QTAILQ_REMOVE(&q->ehci->queues, q, next);
- qemu_free(q);
+ g_free(q);
}
static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr)
*/
for(i = 0; i < NB_PORTS; i++) {
devs[i] = s->ports[i].dev;
- if (devs[i]) {
- usb_attach(&s->ports[i], NULL);
+ if (devs[i] && devs[i]->attached) {
+ usb_detach(&s->ports[i]);
}
}
} else {
s->portsc[i] = PORTSC_PPOWER;
}
- if (devs[i]) {
- usb_attach(&s->ports[i], devs[i]);
+ if (devs[i] && devs[i]->attached) {
+ usb_attach(&s->ports[i]);
}
}
ehci_queues_rip_all(s);
return;
}
- if (dev) {
- usb_attach(&s->ports[port], NULL);
+ if (dev && dev->attached) {
+ usb_detach(&s->ports[port]);
}
*portsc &= ~PORTSC_POWNER;
*portsc |= owner;
- if (dev) {
- usb_attach(&s->ports[port], dev);
+ if (dev && dev->attached) {
+ usb_attach(&s->ports[port]);
}
}
if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
trace_usb_ehci_port_reset(port, 0);
- if (dev) {
- usb_attach(&s->ports[port], dev);
+ if (dev && dev->attached) {
+ usb_attach(&s->ports[port]);
usb_send_msg(dev, USB_MSG_RESET);
*portsc &= ~PORTSC_CSC;
}
* Table 2.16 Set the enable bit(and enable bit change) to indicate
* to SW that this port has a high speed device attached
*/
- if (dev && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
+ if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
val |= PORTSC_PED;
}
}
again = 1;
break;
+ case NLPTR_TYPE_STITD:
+ ehci_set_state(ehci, async, EST_FETCHSITD);
+ again = 1;
+ break;
+
default:
- // TODO: handle siTD and FSTN types
+ /* TODO: handle FSTN type */
fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
"which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
return -1;
return 1;
}
+static int ehci_state_fetchsitd(EHCIState *ehci, int async)
+{
+ uint32_t entry;
+ EHCIsitd sitd;
+
+ assert(!async);
+ entry = ehci_get_fetch_addr(ehci, async);
+
+ get_dwords(NLPTR_GET(entry), (uint32_t *)&sitd,
+ sizeof(EHCIsitd) >> 2);
+ ehci_trace_sitd(ehci, entry, &sitd);
+
+ if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
+ /* siTD is not active, nothing to do */;
+ } else {
+ /* TODO: split transfers are not implemented */
+ fprintf(stderr, "WARNING: Skipping active siTD\n");
+ }
+
+ ehci_set_fetch_addr(ehci, async, sitd.next);
+ ehci_set_state(ehci, async, EST_FETCHENTRY);
+ return 1;
+}
+
/* Section 4.10.2 - paragraph 3 */
static int ehci_state_advqueue(EHCIQueue *q, int async)
{
again = ehci_state_fetchitd(ehci, async);
break;
+ case EST_FETCHSITD:
+ again = ehci_state_fetchsitd(ehci, async);
+ break;
+
case EST_ADVANCEQUEUE:
again = ehci_state_advqueue(q, async);
break;
pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
//pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
- pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); // interrupt pin 3
+ pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);